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Forum - Thread List

Latest Posts

  • Discussion

    Gerber file with different extension

    Category: PCB Design

    By C Shiva

    •

    updated over 13 years ago by C Shiva

    3 replies • 18527 views
  • Discussion

    Property File Syntax (PRP) for Monte Carlo Advance Analysis of a Netlisted Sub-Circuit

    Category: PCB Design

    By NYAlanR

    •

    updated over 13 years ago by NYAlanR

    4 replies • 14555 views
  • Discussion

    pspice or spice models for LP2951(voltage regulator) and DS1809(digital potentiometer)

    Category: PCB Design

    By amal37

    •

    started over 13 years ago

    0 replies • 1311 views
  • Discussion

    Cannot create netlist, CIS 16.3, Win7

    Category: PCB Design

    By drteeter

    •

    updated over 13 years ago by paragc

    1 replies • 13349 views
  • Discussion

    AMS Simulator - DEHDL 16.5

    Category: PCB Design

    By KoolKat

    •

    updated over 13 years ago by KoolKat

    2 replies • 1338 views
  • Discussion

    Trace Tapering

    Category: PCB Design

    By Prapz

    •

    updated over 13 years ago by steve

    1 replies • 14102 views
  • Discussion

    minimizing tracks on one layer, maximizing on the other

    Category: PCB Design

    By slavne

    •

    updated over 13 years ago by slavne

    8 replies • 15730 views
  • Discussion

    Voiding within Package Keepout

    Category: PCB Design

    By Mstrghettorigg

    •

    updated over 13 years ago by steve

    1 replies • 13337 views
  • Discussion

    footprint IPC STANDARD

    Category: PCB Design

    By rinj

    •

    updated over 13 years ago by girish

    6 replies • 20332 views
  • Discussion

    REG:PSM & PAD PATH

    Category: PCB Design

    By girish

    •

    updated over 13 years ago by girish

    2 replies • 1183 views
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