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  • Not Answered

    Thru Pin to Thru Pin DRC Error 0

    14478 views
    7 replies
    Latest over 4 years ago
    by Bejoy Thomas
  • Discussion

    Accessing additional TI libraries for simulation in PSpice

    12034 views
    0 replies
    Started over 4 years ago
    by DesignTech
  • Not Answered

    Adding Color Dialog in Grid Form Using Skill 0

    4714 views
    0 replies
    Started over 4 years ago
    by vimaldevlpr
  • Discussion

    OrCAD - Tip of the Week: Navigating a hierarchical design

    2642 views
    0 replies
    Started over 4 years ago
    by DesignTech
  • Not Answered

    Conversion from OrCAD SDT to Capture V17.2 - Results Unclear 0

    845 views
    0 replies
    Started over 4 years ago
    by Altazi
  • Not Answered

    Are flash pads necessary? 0

    12098 views
    2 replies
    Latest over 4 years ago
    by Noradavis
  • Not Answered

    "Enable Hierarchical Variants" option is disabled Design Entry HDL 0

    1678 views
    0 replies
    Started over 4 years ago
    by markyd
  • Discussion

    SKILL For Composing a Shape enclosing the PAD EDGE of set of Pins

    6011 views
    3 replies
    Latest over 4 years ago
    by DavidJHutchins
  • Discussion

    SKILL program for creating shapes from closed polygon lines.

    8593 views
    2 replies
    Latest over 4 years ago
    by mstaub
  • Not Answered

    Issues with database orcad pcb 17.4 0

    10302 views
    0 replies
    Started over 4 years ago
    by maurisset
  • Discussion

    Allegro – Tip of the week: Reopen Command

    9792 views
    0 replies
    Started over 4 years ago
    by PCBTech
  • Not Answered

    Problem with launching Ultra Librarian after hotfix update(S028) 0

    1368 views
    1 reply
    Latest over 4 years ago
    by steve
  • Discussion

    Putting testpoint out of the board by a script

    9988 views
    1 reply
    Latest over 4 years ago
    by DavidJHutchins
  • Discussion

    PSpice A/D Modelling Application – Create and use models on the fly

    1621 views
    0 replies
    Started over 4 years ago
    by DesignTech
  • Not Answered

    Test point on nets within a hierarchical block that don't have a port in the symbol 0

    2450 views
    1 reply
    Latest over 4 years ago
    by markyd
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