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  • Discussion

    CONCEPT-HDL-NETLIST ERROR Locked

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    1 reply
    Latest over 12 years ago
    by chads108
  • Discussion

    Min_Line_Width Max_Line_Width Locked

    13943 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    Importing .brd into Allegro 16.6 FPGA System Planner: how to connect the comonents? Locked

    13752 views
    0 replies
    Started over 12 years ago
    by ocenblue
  • Discussion

    How to change the default font which is used by the PSpice Model Editor when creating Capture Parts respectively OrCAD Capture Libraries Locked

    18236 views
    4 replies
    Latest over 12 years ago
    by Echinos
  • Discussion

    OrCad Layout on Windows 7 ? Locked

    17817 views
    6 replies
    Latest over 12 years ago
    by Doodle1800
  • Discussion

    Remove(gray out) one single occurence in Orcad Locked

    2067 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    PCB editor name/versions? Locked

    1105 views
    4 replies
    Latest over 12 years ago
    by steve
  • Discussion

    To hold the line on PCB Locked

    5037 views
    1 reply
    Latest over 12 years ago
    by steve
  • Discussion

    how to import 16.5 board file into 16.3 Locked

    13781 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    Waive DRCs report

    15590 views
    4 replies
    Latest over 12 years ago
    by eDave
  • Discussion

    Viewing existing ODB++ data Locked

    21387 views
    2 replies
    Latest over 12 years ago
    by padmaster
  • Discussion

    Import in local CIS database Locked

    14568 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    CIS connected to MySQL database Locked

    17468 views
    4 replies
    Latest over 12 years ago
    by stetag
  • Discussion

    Replicate similar rooms, copy & paste routes in Allegro PCB 16.5 Locked

    2525 views
    2 replies
    Latest over 12 years ago
    by Hossein1357
  • Discussion

    Wirebond and Flip Chip design in SiP to ODB++ output Locked

    14239 views
    0 replies
    Started over 12 years ago
    by Sam Mirza
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