• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Community Search
  • User
Forum - Thread List
  • Discussion

    why the same length? Locked

    14703 views
    3 replies
    Latest over 18 years ago
    by archive
  • Discussion

    Hspice in PCB SI- unable to simulate with MS and vias Locked

    1378 views
    2 replies
    Latest over 18 years ago
    by archive
  • Discussion

    Accessing attachaments

    16516 views
    7 replies
    Latest over 18 years ago
    by archive
  • Discussion

    setup of Valor ODB++ Inside Locked

    18952 views
    3 replies
    Latest over 18 years ago
    by archive
  • Discussion

    Getting the Pin Position in Schematic ???

    12937 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    How to get Pad Attributes

    13589 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    hyp file for Hyperlynex simulation Locked

    13105 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    where are the extracta command files located?

    15992 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    how to import virtuoso gds output in to APD (advanced package designer)

    21265 views
    7 replies
    Latest over 18 years ago
    by archive
  • Discussion

    How to hilight nets or symbols

    12989 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    extracta command line for - Etch Length by Pin Pair

    1196 views
    0 replies
    Started over 18 years ago
    by archive
  • Discussion

    warning: "could not fit symbol" Locked

    3330 views
    3 replies
    Latest over 18 years ago
    by archive
  • Discussion

    Allegro Padstacks; Defined Geometry vs. Flash Locked

    15479 views
    3 replies
    Latest over 19 years ago
    by archive
  • Discussion

    About Design Attributes

    13720 views
    1 reply
    Latest over 19 years ago
    by archive
  • Discussion

    Using .sp file for connector in SigXP Locked

    15279 views
    4 replies
    Latest over 19 years ago
    by archive
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information