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Does termination resistor on differential pair brought mismatch to differential impedance?

Fakhri
I am working on high speed 8 layer HDI design. My design include differential pairs with 100 ohm diff. impedance. I have 100 ohm termination at receiver side for each of these differential pair.
I have crosschecked the impedance of these line in Cadence impedance workflow  and  observed a impedance mismatch at termination resistor location. The usual value of diff impedance is around 100 ohm while at termination resistor, impedance value around 168 ohm.
Could anyone please suggest any solution or trick to tackle this mismatch?
The resistor has smd 0402 package, does this mismatch will degrade my signal quality?
Many thanks!
  • excellon1
    0

    Can you provide the trace and space width of your diff-pair and the height this diff-pair is above a ground or power plane.

    Not really enough information to determine based on what you are asking.

  • Fakhri
    0 in reply to excellon1

    The depth of reference plane (L3) is 0.250mm.

    The track width is 0.127 mm and spacing is 0.110 mm. The copper thickness is  0.047 mm.

  • excellon1
    0 in reply to Fakhri

    In checking your Diff-Pair, I find t is not optimal if one considers ER constant of board say 4 to 5 and variables in the height. Point here is while your math may work out for a certain diff-pair if either the height or er change then the line you think you have is not exactly optimal considering the variables.

    In the workflow they are basically showing you where the impedance discontinuity is showing up so what you would have to take into account is the typical impedance of the segments at the end of the line to fix the issue. In the picture you can see the lines entering the pads are highlighted in red and green.

    You could try the following. Keeping everything as it is now. Make both the green trace and red trace segments wider and re-run the analysis to see what it indicates.

    On a diff-pair there will always be oddities at the end of the line. A good rule of thumb is to consider the pin spacing of say the IC that your diff pair is connecting to and make the diff pair spacing close to this. The advantage is that when you get to the end of the line and you have to go wider on the space to enter the pins there will be less discontinuity. Wider lines in the diff-pair are also better.

    You could also try this diff pair instead if your design can stand it. This will also account for the variable ER & +,- a few mils in stackup height.

    Trace width = 7.5 Mil
    Space = 10 Mil.

    Where the segments enter the pads  and break away from the main line.

    Trace width = 15 Mil
    Space = 25 Mil , that assumes the pn spacing is close to 25 Mil

    One last thing. You see above the trace width of 15 Mil with a space of 25 Mil. The impedance of this is still 100 Ohms Diff. What this does is effectively matches the main line impedance
    to where it branches out and goes into the IC.

    All the best

  • jc teyssier
    0 in reply to excellon1

    Application note from Intel:

    https://www.intel.com/content/www/us/en/programmable/documentation/joc1462311266908.html#joc1463333802645

    In order to avoid impedance problems at resistor location you may open the reference plane under.

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