Stats

  • State Not Answered
  • Replies 17
  • Subscribers 22
  • Views 1600
  • Members are here 0
More Content

Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Renu Vibha

Curious about the latest features? Facing real-world design challenges you’d like to crack faster?

This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them.

Join us here on June 24, 2026 at 7:30 – 8:30 PM IST

Topics

  • PCB & IC Package S-Parameter Model Extraction
  • PDN Voltage Drop Analysis
  • High-Speed Design Simulation

This is your opportunity to:

  • Ask live questions
  • Learn from real use cases
  • Exchange insights with peers

Bring your challenges. Share your perspective. Be part of the conversation.

  • Renu Vibha
    0

    2 days to go! 

    If you’re working with Cadence Sigrity tools or exploring signal and power integrity concepts, this session is a great opportunity to get your queries clarified in real time.

    Bring your questions- we'll bring the experts. 

     

  • Renu Vibha
    0 in reply to Renu Vibha

    We are all set, are you? 

    No matter if you’re working with Cadence Sigrity tools or exploring signal and power integrity concepts, this session is a great opportunity to

    Learn from experts. Ask Questions.Grow your network.

  • ShivaShankarM
    0

    Welcome everyone and thank you for joining today’s Expert Session.

    Please feel free to post your questions any time—we’re here to help.

  • ShivaShankarM
    0
    To get us started, here's a common question:  "How much spacing is enough to reduce crosstalk between high-speed traces?"
    A quick perspective: There isn't a single rule that works for every design. Stackup, trace geometry, rise time, and reference planes all influence coupling behavior.
    What crosstalk challenges have you faced in your projects?
  • EDA Star
    0 in reply to ShivaShankarM

    When performing simultaneous switching noise (SSN) analysis for high-speed memory interfaces like DDR5 using Cadence Sigrity, how do you accurately balance the trade-off between using a full-wave 3D EM extraction versus a hybrid approach (like Sigrity PowerSI) for the package-board composite model, and what specific metrics do you look for to validate that your power delivery network (PDN) isn't degrading signal integrity?

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.