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Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Renu Vibha

Curious about the latest features? Facing real-world design challenges you’d like to crack faster?

This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them.

Join us here on June 24, 2026 at 7:30 – 8:30 PM IST

Topics

  • PCB & IC Package S-Parameter Model Extraction
  • PDN Voltage Drop Analysis
  • High-Speed Design Simulation

This is your opportunity to:

  • Ask live questions
  • Learn from real use cases
  • Exchange insights with peers

Bring your challenges. Share your perspective. Be part of the conversation.

  • CF202606104231
    0

    Why do Engineers use field - solvers like PowerSI instead of rule-of-thumb calculations? 

  • ShivaShankarM
    0 in reply to EDA Star

    Thank you for the question. Based on what you’ve shared, for DDR5 SSN analysis, it’s best to balance full-wave EM and hybrid extraction rather than treating them as alternatives. use Clarity 3D for EM-critical regions (BGA breakouts, vias, package escapes, return-path discontinuities) and PowerSI/SystemSI for the full package-board model after correlating against a representative full-wave subset.

    To ensure the PDN is not degrading SI, monitor PDN impedance vs target impedance, anti-resonance peaks, VDDQ/VSS ripple, eye height/width, DQ–DQS timing margins, setup/hold margins, jitter, and SSN-induced power/ground bounce. Model validation should also include TDR, IL/RL correlation, passivity, and causality checks.

     

  • EDA Star
    0 in reply to EDA Star

    Also..... In Cadence Sigrity PowerDC, how do we run the electrical and thermal simulation together to see how heat changes the copper resistance and affects the voltage drop?

  • ShivaShankarM
    0 in reply to CF202606104231

    Engineers use field solvers because real designs involve complex 3D electromagnetic interactions, coupling, and PDN effects that simple rule-based calculations cannot accurately capture.

  • EDA Star
    0 in reply to ShivaShankarM

    OK. Since you recommended a hybrid flow combining PowerSI and Clarity 3D, how do you handle the port-mapping and reference-ground alignment when stitching the 3D Clarity via-models back into the PowerSI layout to ensure no artificial discontinuities are introduced in SystemSI?

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