Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Welcome everyone and thank you for joining today’s Expert Session.

Please feel free to post your questions any time—we’re here to help.

When performing simultaneous switching noise (SSN) analysis for high-speed memory interfaces like DDR5 using Cadence Sigrity, how do you accurately balance the trade-off between using a full-wave 3D EM extraction versus a hybrid approach (like Sigrity PowerSI) for the package-board composite model, and what specific metrics do you look for to validate that your power delivery network (PDN) isn't degrading signal integrity?

Thank you for the question. Based on what you’ve shared, for DDR5 SSN analysis, it’s best to balance full-wave EM and hybrid extraction rather than treating them as alternatives. use Clarity 3D for EM-critical regions (BGA breakouts, vias, package escapes, return-path discontinuities) and PowerSI/SystemSI for the full package-board model after correlating against a representative full-wave subset.

To ensure the PDN is not degrading SI, monitor PDN impedance vs target impedance, anti-resonance peaks, VDDQ/VSS ripple, eye height/width, DQ–DQS timing margins, setup/hold margins, jitter, and SSN-induced power/ground bounce. Model validation should also include TDR, IL/RL correlation, passivity, and causality checks.

Also..... In Cadence Sigrity PowerDC, how do we run the electrical and thermal simulation together to see how heat changes the copper resistance and affects the voltage drop?

OK. Since you recommended a hybrid flow combining PowerSI and Clarity 3D, how do you handle the port-mapping and reference-ground alignment when stitching the 3D Clarity via-models back into the PowerSI layout to ensure no artificial discontinuities are introduced in SystemSI?

OK. Since you recommended a hybrid flow combining PowerSI and Clarity 3D, how do you handle the port-mapping and reference-ground alignment when stitching the 3D Clarity via-models back into the PowerSI layout to ensure no artificial discontinuities are introduced in SystemSI?

Good question, EDA Star!

Cadence provides a Clarity 3D Cut-and-Stitch flow, where EM-critical regions (such as BGA breakouts, vias, package escapes, etc.) can be solved using the Clarity 3D FEM solver, while the remaining layout is solved using PowerSI's hybrid extraction engine.

To avoid introducing artificial discontinuities, the Clarity and PowerSI regions are stitched together at consistent electrical boundaries with matching signal/reference definitions. The stitched model is then validated using metrics such as TDR continuity, impedance correlation, and IL/RL consistency before performing system-level simulations.

The resulting composite model can be analyzed in Topology Workbench/SystemSI for eye diagrams, jitter, SSN/PDN analysis, timing margin evaluation, and SerDes compliance verification.

Hmmm...This helps... Thank you !