Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

In Sigrity PowerDC, electrical and thermal effects are analyzed using its electro-thermal (ET) simulation capability, which is essential because temperature directly impacts copper resistance and hence IR drop. PowerDC first solves the DC current distribution and IR drop, computes the resulting Joule heating, updates the copper conductivity/resistance based on temperature, and then re-solves the electrical network. This iterative process continues until both temperature and voltage results converge.

The key outputs are temperature hotspots, current density, copper temperature rise, resistance increase, and the resulting IR drop/voltage at sinks, allowing you to directly quantify how self-heating impacts power delivery.

THank you...

Sometimes in high-current designs, the loop keeps heating up copper, the resistance keeps rising, and the simulation fails to converge (it errors out). When PowerDC fails to reach equilibrium, what are the best design steps to fix this thermal runaway issue?

Good question, EDA Star!

Cadence provides a Clarity 3D Cut-and-Stitch flow, where EM-critical regions (such as BGA breakouts, vias, package escapes, etc.) can be solved using the Clarity 3D FEM solver, while the remaining layout is solved using PowerSI's hybrid extraction engine.

To avoid introducing artificial discontinuities, the Clarity and PowerSI regions are stitched together at consistent electrical boundaries with matching signal/reference definitions. The stitched model is then validated using metrics such as TDR continuity, impedance correlation, and IL/RL consistency before performing system-level simulations.

The resulting composite model can be analyzed in Topology Workbench/SystemSI for eye diagrams, jitter, SSN/PDN analysis, timing margin evaluation, and SerDes compliance verification.

Hmmm...This helps... Thank you !

If an electro-thermal simulation fails to converge, it's often an indication of a real design issue rather than just a simulation issue. The first things you should investigate are current-density hotspots, excessive IR drop, localized temperature rise, and PDN bottlenecks.

Typical fixes include:

• Increasing copper width/thickness
• Adding more vias or parallel current paths
• Improving cooling (thermal vias, heatsinks, airflow)
• Reducing load concentration and spreading current more evenly

In PowerDC, focus on regions showing the highest current density, temperature rise, and resistance increase, as these are usually the root causes preventing convergence.