Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Welcome everyone and thank you for joining today’s Expert Session.

Please feel free to post your questions any time—we’re here to help.

When performing simultaneous switching noise (SSN) analysis for high-speed memory interfaces like DDR5 using Cadence Sigrity, how do you accurately balance the trade-off between using a full-wave 3D EM extraction versus a hybrid approach (like Sigrity PowerSI) for the package-board composite model, and what specific metrics do you look for to validate that your power delivery network (PDN) isn't degrading signal integrity?

Thank you for the question. Based on what you’ve shared, for DDR5 SSN analysis, it’s best to balance full-wave EM and hybrid extraction rather than treating them as alternatives. use Clarity 3D for EM-critical regions (BGA breakouts, vias, package escapes, return-path discontinuities) and PowerSI/SystemSI for the full package-board model after correlating against a representative full-wave subset.

To ensure the PDN is not degrading SI, monitor PDN impedance vs target impedance, anti-resonance peaks, VDDQ/VSS ripple, eye height/width, DQ–DQS timing margins, setup/hold margins, jitter, and SSN-induced power/ground bounce. Model validation should also include TDR, IL/RL correlation, passivity, and causality checks.

Also..... In Cadence Sigrity PowerDC, how do we run the electrical and thermal simulation together to see how heat changes the copper resistance and affects the voltage drop?

OK. Since you recommended a hybrid flow combining PowerSI and Clarity 3D, how do you handle the port-mapping and reference-ground alignment when stitching the 3D Clarity via-models back into the PowerSI layout to ensure no artificial discontinuities are introduced in SystemSI?

In Sigrity PowerDC, electrical and thermal effects are analyzed using its electro-thermal (ET) simulation capability, which is essential because temperature directly impacts copper resistance and hence IR drop. PowerDC first solves the DC current distribution and IR drop, computes the resulting Joule heating, updates the copper conductivity/resistance based on temperature, and then re-solves the electrical network. This iterative process continues until both temperature and voltage results converge.

The key outputs are temperature hotspots, current density, copper temperature rise, resistance increase, and the resulting IR drop/voltage at sinks, allowing you to directly quantify how self-heating impacts power delivery.

THank you...

Sometimes in high-current designs, the loop keeps heating up copper, the resistance keeps rising, and the simulation fails to converge (it errors out). When PowerDC fails to reach equilibrium, what are the best design steps to fix this thermal runaway issue?

THank you...

Sometimes in high-current designs, the loop keeps heating up copper, the resistance keeps rising, and the simulation fails to converge (it errors out). When PowerDC fails to reach equilibrium, what are the best design steps to fix this thermal runaway issue?

If an electro-thermal simulation fails to converge, it's often an indication of a real design issue rather than just a simulation issue. The first things you should investigate are current-density hotspots, excessive IR drop, localized temperature rise, and PDN bottlenecks.

Typical fixes include:

• Increasing copper width/thickness
• Adding more vias or parallel current paths
• Improving cooling (thermal vias, heatsinks, airflow)
• Reducing load concentration and spreading current more evenly

In PowerDC, focus on regions showing the highest current density, temperature rise, and resistance increase, as these are usually the root causes preventing convergence.

That make sa lot of sense. I actually facd a similar issue recently on a dense board where the simulation wouldn't converge because of a tight current bottleneck near a small power pin. I cudnot widen the copper trace because of layout space, and adding more vias wasn't possible due to routing rules. In a tough spot like that where you can't just 'add more copper,' what is the next best trick in PowerDC to help a designer find a creative way out?"