Got Questions on Sigrity? Let’s Answer Them—LIVE on Wednesday, June 24th

Welcome everyone and thank you for joining today’s Expert Session.

Please feel free to post your questions any time—we’re here to help.

When performing simultaneous switching noise (SSN) analysis for high-speed memory interfaces like DDR5 using Cadence Sigrity, how do you accurately balance the trade-off between using a full-wave 3D EM extraction versus a hybrid approach (like Sigrity PowerSI) for the package-board composite model, and what specific metrics do you look for to validate that your power delivery network (PDN) isn't degrading signal integrity?

THank you...

Sometimes in high-current designs, the loop keeps heating up copper, the resistance keeps rising, and the simulation fails to converge (it errors out). When PowerDC fails to reach equilibrium, what are the best design steps to fix this thermal runaway issue?

Good question, EDA Star!

Cadence provides a Clarity 3D Cut-and-Stitch flow, where EM-critical regions (such as BGA breakouts, vias, package escapes, etc.) can be solved using the Clarity 3D FEM solver, while the remaining layout is solved using PowerSI's hybrid extraction engine.

To avoid introducing artificial discontinuities, the Clarity and PowerSI regions are stitched together at consistent electrical boundaries with matching signal/reference definitions. The stitched model is then validated using metrics such as TDR continuity, impedance correlation, and IL/RL consistency before performing system-level simulations.

The resulting composite model can be analyzed in Topology Workbench/SystemSI for eye diagrams, jitter, SSN/PDN analysis, timing margin evaluation, and SerDes compliance verification.

Hmmm...This helps... Thank you !

If an electro-thermal simulation fails to converge, it's often an indication of a real design issue rather than just a simulation issue. The first things you should investigate are current-density hotspots, excessive IR drop, localized temperature rise, and PDN bottlenecks.

Typical fixes include:

• Increasing copper width/thickness
• Adding more vias or parallel current paths
• Improving cooling (thermal vias, heatsinks, airflow)
• Reducing load concentration and spreading current more evenly

In PowerDC, focus on regions showing the highest current density, temperature rise, and resistance increase, as these are usually the root causes preventing convergence.

That make sa lot of sense. I actually facd a similar issue recently on a dense board where the simulation wouldn't converge because of a tight current bottleneck near a small power pin. I cudnot widen the copper trace because of layout space, and adding more vias wasn't possible due to routing rules. In a tough spot like that where you can't just 'add more copper,' what is the next best trick in PowerDC to help a designer find a creative way out?"

That make sa lot of sense. I actually facd a similar issue recently on a dense board where the simulation wouldn't converge because of a tight current bottleneck near a small power pin. I cudnot widen the copper trace because of layout space, and adding more vias wasn't possible due to routing rules. In a tough spot like that where you can't just 'add more copper,' what is the next best trick in PowerDC to help a designer find a creative way out?"