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SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here  on August 19th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

  • 0 in reply to CF202606104231

    Thank you for the question. In real-world PCB and package design, S-parameters are used to characterize how signals propagate through interconnects, while return loss (S11) is used to measure how much signal energy is reflected back due to impedance discontinuities.

    For example, in a DDR5 channel, engineers can extract S-parameters for the traces, vias, connectors, and package and evaluate return loss across the operating frequency range. If excessive reflections are identified, the routing or via structure can be optimized before fabrication. This helps reduce SI issues during hardware bring-up and increases the likelihood of a successful first prototype spin.

  • 0

    Thank you for hosting. One question… how to prevent per layout model from giving a false sense of security when stack up definitions change mid stream ?

  • 0

    Can you share example where analysing insertion loss (s21) helped identify and resolve a signal integrity in a high speed design? 

  • 0 in reply to EDAHut

    Thank you for the question.
    To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps:

    1. Correctly Model Devices: Ensure that all devices are accurately modeled. This is crucial for the validity of pre-layout simulations.
    2. Reassess Design Constraints: After any changes to the stackup, reassess the design constraints that were initially applied. This helps in identifying any new requirements or adjustments needed.
    3. Utilize Model Assignment Utility: Use the Model Assignment utility to associate device models with schematic components. This ensures that the updated stackup is reflected in the simulations.
    4. Iterative Analysis: Conduct iterative analyses after stackup modifications. This allows for adjustments based on the new stackup configuration and ensures that the results remain relevant.
    5. Documentation and Archiving: Keep detailed records of all changes and their impacts on SI results. This aids in tracking the evolution of the design and understanding the implications of stackup changes.

    By following these practices, you can ensure that your pre-layout SI results remain valid and reliable throughout the design process

  • 0 in reply to CF202606104231

    Thank you for the question.

    A typical example is a high-speed PCIe or SerDes channel where the eye diagram fails to meet the required margin. By analyzing S21 (insertion loss), engineers can identify excessive channel attenuation at higher frequencies. The root cause is often excessive trace length, via discontinuities, connectors, or a high-loss dielectric material.
    After optimizing the channel geometry or selecting a lower-loss stackup, the insertion loss improves, leading to better signal quality and improved eye opening. Therefore, S21 is commonly used to verify that the channel meets its loss budget and can support the target data rate before manufacturing.

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