SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha 20 days ago

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here on August 19^th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

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AK20250609765 4 days ago in reply to EDAHut +1

Thank you for the question. To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps: Correctly Model Devices: Ensure…

0 EDAHut 4 days ago in reply to AK20250609765

Helpful thanks
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0 CF202606104231 4 days ago

What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some light
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0 EDAHut 4 days ago

Where does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?
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0 cistheta07 4 days ago

In a high-speed DDR or SerDes design, impedance may be within specification, yet signal integrity issues can still occur. What layout-related factors should be investigated to identify the root cause before running detailed simulations?
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0 AK20250609765 4 days ago in reply to cistheta07

Thank you for the question. Before running detailed SI simulations, I would recommend using the PowerSI ERC - Trace Imp/Cpl/Ref Check workflow. While impedance may be within specification, SI issues can still arise from excessive coupling, missing or discontinuous reference planes, and localized routing violations. The ERC workflow automatically checks these conditions and reports violations through detailed tables and layout overlays, making it easy to identify the exact trace segments responsible for potential SI degradation. This allows layout issues to be corrected early, reducing simulation iterations and improving overall design quality.
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SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

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