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Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

Hello Experts,

Is there a way to perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment?

Specifically, can the tool automatically detect issues such as floating nodes, short circuits, and open circuits during translation, and provide warnings or mark the error locations? Additionally, is there a TCL command available to enable this validation in workflows?

Thank you.

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