Automated Layout Validation During PCB/Package Translation in Sigrity & Clarity

Hi Cistheta,

Yes. Sigrity and Clarity provide a Layout Validation feature that can automatically perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment.

When Layout Validation is enabled, the tool automatically runs a comprehensive set of error-checking functions during the translation process and can detect issues such as:

• Floating Nodes
• Geometry Errors
• Short Circuits
• Open Circuits

In addition to detecting these issues, the tool can:

• Mark error locations directly on the layout
• Display warning messages for detected short circuits
• Control warning output limits
• Ignore specific warnings, such as short circuits between REF_plane and GND nets

The feature can be enabled through:
Tools → Options → Edit Options → Translator → Settings → Layout Validation

Once enabled, validation is performed automatically during the translation of supported databases such as Cadence Allegro (.brd), ODB++, and Gerber designs into the Sigrity/Clarity environment.

For automation workflows, the following TCL command can be used:

sigrity::spdif_option LayoutValidation 1

1 = Enable Layout Validation
0 = Disable Layout Validation

This option acts as a master validation switch, automatically executing the available layout integrity checks and applying the configured error-reporting behavior during translation.

Best regards,
Alok

Hi Cistheta,

Yes. Sigrity and Clarity provide a Layout Validation feature that can automatically perform layout integrity checks during PCB or IC Package translation into the Sigrity/Clarity environment.

When Layout Validation is enabled, the tool automatically runs a comprehensive set of error-checking functions during the translation process and can detect issues such as:

• Floating Nodes
• Geometry Errors
• Short Circuits
• Open Circuits

In addition to detecting these issues, the tool can:

• Mark error locations directly on the layout
• Display warning messages for detected short circuits
• Control warning output limits
• Ignore specific warnings, such as short circuits between REF_plane and GND nets

The feature can be enabled through:
Tools → Options → Edit Options → Translator → Settings → Layout Validation

Once enabled, validation is performed automatically during the translation of supported databases such as Cadence Allegro (.brd), ODB++, and Gerber designs into the Sigrity/Clarity environment.

For automation workflows, the following TCL command can be used:

sigrity::spdif_option LayoutValidation 1

1 = Enable Layout Validation
0 = Disable Layout Validation

This option acts as a master validation switch, automatically executing the available layout integrity checks and applying the configured error-reporting behavior during translation.

Best regards,
Alok