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  • Discussion

    Using ix and iy console commands with axlEnterPoint or axlEnterEvent

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    Latest over 7 years ago
    by DavidJHutchins
  • Discussion

    Spacing between shapes Locked

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    Latest over 7 years ago
    by JohnSheley
  • Discussion

    Genus Synthesis - Cost Groups Locked

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    Started over 7 years ago
    by Heaton15
  • Discussion

    Is it possible to define interchangeable part numbers in a BOM? Locked

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    7 replies
    Latest over 7 years ago
    by EvanShultz
  • Discussion

    How to convert complete PCB library from 16.6 to 17.2 formats Locked

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    2 replies
    Latest over 7 years ago
    by DavidJHutchins
  • Discussion

    Accidental annotation of schematic, update net in PCB editor? Locked

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    0 replies
    Started over 7 years ago
    by Ruddwijk
  • Discussion

    Power IR/EM vs Voltus-Fi Locked

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    5 replies
    Latest over 7 years ago
    by AndreyVolk
  • Discussion

    Border page lock Locked

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    Started over 7 years ago
    by P ten Wolde
  • Discussion

    Replace Cache useing TCL command Locked

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    0 replies
    Started over 7 years ago
    by Ea222
  • Discussion

    low pass filter in viva/calculator Locked

    21119 views
    17 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Adding same (fully correlated) Phase-noise to two LO paths Locked

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    11 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Virtuoso XL finish wire function Locked

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    4 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    modgen: best way to change device m-factor? Locked

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    2 replies
    Latest over 7 years ago
    by analogfan
  • Discussion

    Cadence Custom Layout for beginners -RF IC design Locked

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    1 reply
    Latest over 7 years ago
    by Quek
  • Discussion

    best resources and RAKs on Verilog A, Verilog AMS and AMS designer, ADE assembler test/verification and SimVision Locked

    2721 views
    3 replies
    Latest over 7 years ago
    by Andrew Beckett
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