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Forum - Thread List
  • Discussion

    Merging an overlapping shapes on Package Geometry

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  • Discussion

    adding ahdl parameters to schematic Locked

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  • Discussion

    dialog interactive window noise summary Locked

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  • Discussion

    Property for when writes to a fifo stop Locked

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  • Discussion

    Is vector replay supported on Palladium? Locked

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  • Discussion

    output pin connected to power/ground net Locked

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  • Discussion

    Impedance Probe? Locked

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  • Discussion

    Impedance Probe? Locked

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  • Discussion

    To learn SystemVerilog, which Book (Basic to ADvance) Locked

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    12 replies
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  • Discussion

    Simulation topics also discussed in this forum now Locked

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  • Discussion

    Functional Coverage in Transaction Class Locked

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  • Discussion

    Hi Locked

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  • Discussion

    Using the Forum Locked

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    5 replies
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  • Discussion

    Simulating SOI circuit using Spectre Locked

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    Started over 18 years ago
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  • Discussion

    Any way to report logic names of buffers/inverters ripped up during PlaceDesign? Locked

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    Latest over 18 years ago
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