• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Not Answered

    Restore/undelete Refdes in OrCAD PCB? 0

    3494 views
    2 replies
    Latest over 3 years ago
    by steve
  • Discussion

    All Layer Visible Locked

    10240 views
    2 replies
    Latest over 3 years ago
    by StanleyChiu
  • Not Answered

    Allegro 17.2 and 17.2 Drill chart of drill rectangular slot columns unfilled 0

    8288 views
    0 replies
    Started over 3 years ago
    by smah
  • Discussion

    How to simulate portion of the circuit with pre layout models & remaining circuit with post layout models? Locked

    3115 views
    4 replies
    Latest over 3 years ago
    by VenkateshTati
  • Discussion

    [Verilog-A/AMS] Using a for loop to instantiate module Locked

    11268 views
    4 replies
    Latest over 3 years ago
    by delgsy
  • Discussion

    [SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output Locked

    4715 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    error happen when using Debugging UVM with simvision Locked

    12227 views
    2 replies
    Latest over 3 years ago
    by galenxiao
  • Discussion

    Can I pass value between runs in Transient Noise simulation? Locked

    11120 views
    6 replies
    Latest over 3 years ago
    by FormerMember
  • Not Answered

    Add tcl script to menu bar in Capture CIS 17.2 0

    5596 views
    1 reply
    Latest over 3 years ago
    by Diego cmre
  • Not Answered

    Orcad Capture TCL scripting documentation 0

    6200 views
    0 replies
    Started over 3 years ago
    by Diego cmre
  • Discussion

    Assert device check w/ pss.hb Locked

    9474 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    differential pair spacing to to other nets

    10963 views
    2 replies
    Latest over 3 years ago
    by avant
  • Discussion

    Simulating a s-par file created with ADS (advanced methodology) Locked

    11666 views
    2 replies
    Latest over 3 years ago
    by amitG22
  • Discussion

    Calculator error on arithmetic operation on the reading of digital bus Locked

    9364 views
    2 replies
    Latest over 3 years ago
    by FormerMember
  • Discussion

    LayoutXL creating auto connectivity of custom cell Locked

    9598 views
    5 replies
    Latest over 3 years ago
    by Andrew Beckett
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information