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Forum - Thread List
  • Discussion

    PVS Extraction Issue - Not finding PVS or QRC tab in Virtuoso Layout to do parasitic extraction Locked

    9280 views
    13 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Package Library download issue Locked

    10141 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    .cdsinit setting to open assembler/explorer, by default, on a new window Locked

    1948 views
    3 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    paralleled inductors in cadence virtuoso Locked

    15336 views
    6 replies
    Latest over 4 years ago
    by zuiying
  • Discussion

    DE HDL Printing Net Attributes Locked

    9261 views
    0 replies
    Started over 4 years ago
    by tmd63
  • Discussion

    Aliases nested too deeply Locked

    9832 views
    0 replies
    Started over 4 years ago
    by charliejuk
  • Discussion

    Copper pull back Locked

    10993 views
    1 reply
    Latest over 4 years ago
    by excellon1
  • Discussion

    How to launch Stratus GUI Locked

    12315 views
    0 replies
    Started over 4 years ago
    by gdnagendra
  • Discussion

    How to get numbers/parameters from a user defined dialog box Locked

    2260 views
    4 replies
    Latest over 4 years ago
    by HaolinCong
  • Discussion

    Search for all instances of a specific cell within a hierarchy Locked

    14357 views
    3 replies
    Latest over 4 years ago
    by FormerMember
  • Discussion

    ROHS FPGA in a leaded process Locked

    9139 views
    0 replies
    Started over 4 years ago
    by atoddrich
  • Discussion

    Trigger Function for Popup Windows Locked

    10782 views
    2 replies
    Latest over 4 years ago
    by kdolan
  • Discussion

    Allegro footprint .dra file version too old to import into Altium?

    13042 views
    4 replies
    Latest over 4 years ago
    by hobbskw
  • Discussion

    different results from spice in Locked

    11183 views
    2 replies
    Latest over 4 years ago
    by MReza123
  • Discussion

    veriloga integer input to 32-bit address output has a strnage error/how to debug/where to find the latest veriloga reference documents? Locked

    4586 views
    5 replies
    Latest over 4 years ago
    by monglebest2022
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