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Forum - Thread List
  • Discussion

    Problems with transistor operation point info in transient analysis Locked

    10793 views
    2 replies
    Latest over 4 years ago
    by greywanderer
  • Discussion

    Re-running a particular iteration of the montecarlo sims Locked

    12661 views
    5 replies
    Latest over 4 years ago
    by greywanderer
  • Discussion

    Allegro Project Manager display error Locked

    11179 views
    1 reply
    Latest over 4 years ago
    by steve
  • Discussion

    Same net different trace width Locked

    10179 views
    1 reply
    Latest over 4 years ago
    by steve
  • Discussion

    When auto-connecting a trace from a via how do you stop the software from changing netnames when a shape is on that layer.

    10480 views
    2 replies
    Latest over 4 years ago
    by mcatramb91
  • Discussion

    Measuring XStream performance in Virtuoso Locked

    9732 views
    0 replies
    Started over 4 years ago
    by knowledgeseeker
  • Not Answered

    what is the "convert" in part window of CIS explorer 0

    5524 views
    3 replies
    Latest over 4 years ago
    by CSPanMan
  • Discussion

    Parameterizable Voltage Controlled Oscillator Model Locked

    14531 views
    5 replies
    Latest over 4 years ago
    by FormerMember
  • Discussion

    Stack-up or Cross-section changes every time I export physical from Deign Entry HDL to Allegro Editor Locked

    9634 views
    0 replies
    Started over 4 years ago
    by Fakhri
  • Discussion

    Can I make my custom script transparent to the "undo" functionality? Locked

    578 views
    0 replies
    Started over 4 years ago
    by jriad
  • Discussion

    Generating Liberty (.lib) File From Verilog-A Table Model Locked

    13804 views
    3 replies
    Latest over 4 years ago
    by Guangjun Cao
  • Discussion

    How to add stop layers to annotation browser? Locked

    9640 views
    0 replies
    Started over 4 years ago
    by 94d33m
  • Discussion

    teardrop (fillet) question

    10413 views
    2 replies
    Latest over 4 years ago
    by masamasa
  • Discussion

    Which way of getting the target fundamental frequency is correct after simulating a VCO design? Locked

    20791 views
    6 replies
    Latest over 4 years ago
    by FormerMember
  • Discussion

    How to define a socket header between PCB and plugin module?

    7189 views
    3 replies
    Latest over 4 years ago
    by excellon1
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