How to ignore FILL cells from Encounter in LVS Assura?

I wouldn't have expected that you need to ignore these at all. In fact you shouldn't really ignore them because then it will not use any routing inside those cells.

These cells aren't in the Verilog, I assume? If so, I am assuming you're not specifying ?dspfCells and if you are, the fill cells aren't in the list of DSPF cells?

Andrew.

Hi Andrew, thanks for reply.

 Here are the things:

1) Those cells *ARE* in Verilog (or in physical Verilog produced by encounter after routing and FILLing is done)

2) Reason I decided to Ignore them is because the LVS was saying something like "FILL1,FILL2,NWSX" *not defined*

 My problem starts from that bigger thread nearby, where Alex Soyer was trying to help me. I thought that I am almost done, and just that last step left with those cells, and all I need to do is to figure out the way to make LVS ignore them.

But again, bigger problem is:

I managed to get routing done properly in Encounter, I managed to get Layout import to Virtuoso Layout environment properly, I managed to get the clean DRC, but I *cannot manage* to get LVS working, because of reason stated above. which is what pushed me to start figuring out how to ignore those cells.

also: I do LVS over the Imported clean DRC'ed layout by checking against the Physical Verilog produced by encounter.

I am showing below the commands from Encounter which I used to generate physical verilog final7.v, which was used by LVS against the imported Layout. Maybe you can now get a better feeling of why it doesnt want to do LVS normally and throws those errors at me. 

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The following commands:

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saveNetlist -excludeCellInst {FILL1 FILL2 NWSX} -includePowerGround final7.v

saveNetlist -excludeCellInst {FILL1 FILL2 NWSX} -phys final7.v

saveNetlist -includePhysicalInst -excludeCellInst {FILL1 FILL2 NWSX} -includePowerGround final7.v

saveNetlist -includePhysicalInst -includePowerGround -excludeCellInst {FILL1 FILL2 NWSX} final7.v

Result in following errors in Assura LVS log:

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Preprocessing layout network phase 2

*ERROR* Device 'nfet(MOS)' on Layout is unbound to any Schematic device.

*ERROR* Device 'pfet(MOS)' on Layout is unbound to any Schematic device.

*ERROR* Device 'subc(RES)' on Layout is unbound to any Schematic device.

*ERROR* UnBound devices found.

Info: All devices must be bound or filtered for comparision to be run.

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************************************************

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The following commands:

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saveNetlist -phys final7.v

Result in following errors in Assura LVS log:

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Top cell 'refleks_switcher' specified, starting from specified point...

*ERROR* cell 'FILL1' is not defined.

*ERROR* cell 'NWSX' is not defined.

*ERROR* cell 'FILL2' is not defined.

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************************************************

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The following commands:

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saveNetlist -phys -excludeLeafCell final7.v

saveNetlist -excludeLeafCell -includePhysicalInst -excludeCellInst {FILL1 FILL2 NWSX} final7.v

Result in following errors in Assura LVS log:

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Top cell 'refleks_switcher' specified, starting from specified point...

*ERROR* cell 'DFF_E' is not defined.

*ERROR* cell 'NOR2_E' is not defined.

*ERROR* cell 'INVERTBAL_E' is not defined.

*ERROR* cell 'INVERTBAL_H' is not defined.

*ERROR* cell 'MUX21I_D' is not defined.

*ERROR* cell 'OA21_I' is not defined.

*ERROR* cell 'OAI21_C' is not defined.

*ERROR* cell 'AND4_E' is not defined.

*ERROR* cell 'AO22_B' is not defined.

*ERROR* cell 'OR4_E' is not defined.

*ERROR* cell 'AND2_F' is not defined.

*ERROR* cell 'NAND2_F' is not defined.

*ERROR* cell 'INVERT_I' is not defined.

*ERROR* cell 'NOR2_D' is not defined.

*ERROR* cell 'XOR2_C' is not defined.

*ERROR* cell 'INVERT_H' is not defined.

*ERROR* cell 'XNOR2_C' is not defined.

*ERROR* cell 'INVERT_E' is not defined.

*ERROR* cell 'OR2_I' is not defined.

*ERROR* cell 'AOI21_C' is not defined.

*ERROR* cell 'INVERT_F' is not defined.

*ERROR* cell 'FILL1' is not defined.

*ERROR* cell 'NWSX' is not defined.

*ERROR* cell 'FILL2' is not defined.

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So the whole business here is to be able to figure out the right way to do LVS vs my Imported layout from Encounter. And again, the layout from encounter was imported perfectly, has no DRC errors and has all cells and connections in it, and is viewed just great in Virtuoso Layout view. I just cannot get the LVS to work.

Any ideas? 

Hi Kabal,

Andrew tipped me off on this and thought I might be able to help. Let me firts consider the "cell is not defined" issue...

Now. I'm not is possesion of all the facts but you metion the physical verilog. Now what about the cell subckt descriptions? Typically these would be included as cdl. Do you have the cell subckt netlist also specified in your LVS run?

N.B. For a sign-off LVS there is no way you can risk using ignoreCell. You may not be at tape-out stage yet, but down the line you do not want to have to fix this part of the flow when timescale pressures apply.

Next...
*ERROR* Device 'nfet(MOS)' on Layout is unbound to any Schematic device.
Again this is indicitive of missing subckt descriptions. The cdls subckt will include the devices.

As a precursor to sign-off LVS it would be possible to blakck box the std cells.This is a valid approach to speed up LVS iterations. For Assura there is often some rliance on the foundry correctly coding the LVS rules to support black box. But this may be an interim solution prior to including the subcircuits.

Hope that helps.

Rob.

hey RobMan,

I know this thread is extremely old, but I'm encountering a similar issue when running the 45nm RFSOI process from GF.  I had to run the LEF flow through Innovus due to issues with it needing a special license on this process, but after completing the P&R, I exported the layout into virtuoso.  The layout looks good and I use the physical netlist export command from Innovus to get my Verilog netlist.  I then use this with my cdl net lists for the io and standard cells to generate my spice netlist to compare in virtuoso for LVS.  the cdl SUBCKT for the filler cells were not defined, so I created some simple ones that include just VDD and VSS pins and then convert the Verilog netlist into a spice netlist that references all of the cdl files.  After doing all of this, when I try to run lvs, the layout and spice netlist have the filler cells, but the layout states that it is missing the instance.  Any ideas would be helpful

There is an Article which provides on way to handle this...

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nWdhEAE&pageName=ArticleContent

Hope that helps.

Rob.