Simulation Problem

I drew the layout using cadence virtuoso. I don't get any error except DRC check density error. In the same patch, LVS check comparison result clear appears, there is only 1 stamping conflict warning. Thinking that these would not be a problem, I tried to simulate it with the test schematic, but the VT("/P) graph does not oscillate when it should be oscillate. I did run xact to understand the problem. I first ran the output extraction type in c++. Then i tried RCC and R . In the C+CC, my VT("/P) graph is working good, its oscillate. But RCC and R graphs does not oscillate . I think the The problem comes from the resistance. To solve this problem, I shortened the length and increased the width of my links. I also changed the reltol and vabstol values but still i have same problem with RCC and R extraction type. I would be very grateful if you could help me to solve this problem.

LVS Warning:  Stamping Conflict in SCONNECT- Multiple source nets stamp one target net.

         Net ground is selected for stamping .

         Rejected nets: 86 87 

If i click on the net 86 , it shows the link I added below. which is transistor.  If 87 is net, another transistor of the same shape is connected to 86. Also, In this transistor dont have ground connection. Why it gives the error related with ground "Net ground is selected for stamping ."

  • You asked the same question (in essence) in this post: LVS warning related with sampling conflicts (I just noticed that it's in an inappropriate forum, since this forum is for issues with the forum itself not for technical questions). I would move the posts, but I've already answered your previous post and you didn't respond to that - just asked the question again, slightly differently, still without enough information (see my answer to your previous post).


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