Breakfast Bytes Blogs

On January 21 from 8:00am to 11:00am (PST), Cadence and Arm are presenting a joint CadenceCONNECT event Building Arm Compute with Cadence Digital Full Flow for Best PPA. Of course, it will be a virtual event, although there will be live Q&A after each session.

As you probably know, Arm has a wide range of processors going from simple microcontrollers like the Cortex-M0 all the way up to the data center-class Cortex-X1. (For more details on the Cortex-X1, which Arm presented late last year at the Linley Processor Conference, see my post Arm Goes for It.) To realize these designs in silicon requires the best possible design flow for synthesis and physical implementation. This is true whether it is optimizing a simple processor for the lowest possible power and area, or optimizing a high-end processor for ultimate performance. And the best possible design flow is the Cadence Digital Full Flow based around Genus synthesis, Innovus physical design, and the integrated signoff engines.

This event is focused on the high end, though: the Cortex-X1, Cortex-A78, and the Neoverse processors. These were created by Arm to be manufactured in leading-edge processes, so in addition to being large, complex processors in their own right, there are also challenges at the process level. These require synthesis to be more aware of physical issues than in the past, and physical design to be able to do richer transformations on the netlist than just resizing buffers. For details on that see my posts Digital Full Flow for 5/7nm and WEAA EDA/IP Product of the Year: Digital Full Flow with iSpatial Technology.

To give you an idea of the complications of advanced-node processes, here is what Yufeng Luo, who will be giving the Cadence keynote at the event, had to say when I talked to him about 3nm design. You can read that post at Optimized Digital Design, Implementation, and Signoff on TSMC N3. He listed some of the challenges (there are more!):

New transistors
New design rules
New multi-patterning requirements (yes, even with EUV)
Process variability
More corners and power modes
Threshold voltage levels
Wire resistance scaling issues
Timing closure with target PPA
IC packaging complexity (More than Moore)

The event brings together Cadence and Arm technology users and experts to learn more about how you can efficiently implement your Arm-based SoCs with the Cadence digital full-flow solution and reach your power, performance, and area (PPA) targets.

The agenda for the day is as follows:

• 08:00am PST - Arm Keynote - Collaboration in a Time of Change (Dermot O'Driscoll, VP Product Solutions, Infrastructure)
• 08:20am PST - Cadence Keynote - Building Arm Total Compute for Optimal Performance Within Power Budgets (Yufeng Luo, VP Research & Development)
• 08:40am PST - How We Pushed Largest 5nm High-Performance Arm Core to 4GHz Frequency
• 09:10am PST - Divide and Conquer:  Hierarchical Methodology to Reduce TAT by 30% or More on Arm’s High-Performance CPU
• 09:40am PST - Delivering Best-in-Class Low Power for Arm Cortex-A78 Mobile 7nm CPU Using the Cadence Digital Flow
• 10:10am PST - Arm Neoverse CPU Advanced Timing Signoff with Tempus PI Technology 
• 10:40am PST - Cloud-Based Characterization with Cadence Liberate Trio Characterization Suite and Amazon EC2 M6g Instances Powered by Arm-based AWS Graviton2

There will be a live Q&A after each presentation.

Fun Fact

If you google "arm cadence" you will get lots of information about cycling. In cycling, "cadence" means the rate at which you turn the pedals. If you want to measure this, you typically use a device that basically consists of a magnet on the pedals, actually on the "crank arm", along with a sensor that notices each time the magnet goes past. This magnet seems to be called a "crank arm cadence magnet'. That has both Arm and Cadence in it, and they are next to each other, so too tempting for Google. You do get lots of references to Arm and Cadence, too, including several Breakfast Bytes posts.

Learn More

Learn more on the event page for Building Arm Compute with Cadence Digital Full Flow for Best PPA, which includes a link for registration.

Or you can go straight to register.

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