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It is the 57th Design Automation Conference later this month from July 20 to 24. Of course, it is a "virtual experience". Apart from being virtual, many of the trappings of the conference remain: keynotes, SKY talks, tech talks, tutorials, academic tracks. Even networking and happy hour at the end of each day (except you have to BYOB, of course).
There is a keynote every day that runs from 9:20am to 10:00am. I have seen some of the keynote speakers before, so when appropriate I've given a link to last time I wrote about them, so you can go the keynote already knowledgeable about the area.
The first morning, Monday, July 20, opens with a keynote by Philip Wong, who is both a professor at Stanford and the chief scientist at TSMC. His keynote is titled Semiconductor Technology: A System Perspective. I assume it will be a variation of his keynote that I attended at last summer's HOT CHIPS keynote. Historically, the semiconductor industry has used the minimum gate-length of a transistor as the measure of technology advancement (and, until FinFET, it was pretty much the actual drawn gate-length—but now with modern transistors, there really isn't anything 7nm on a 7nm process). In the future, Dr Wong thinks that we will use a three-prong metric consisting of logic density (LD), memory bit density (DM), and interconnect density between logic and memory (DC). DL and DM will increase more slowly than historical trends, so the primary driver of technology advance is going to be interconnect. For the last time I wrote about TSMC's process and manufacturing roadmap, see my post from last year: TSMC OIP: Process Status.
Calista is the CEO of the RISC-V Foundation and so, unsurprisingly, she will be talking about RISC-V Revolution and Momentum. I interviewed her years ago when she was doing the less rewarding task of heading up OpenPower and trying to spread usage of the PowerPC architecture. She will give the second-day keynote on Tuesday, July 21. If you need a background on RISC-V, then my most recent post from December last year is What's Happening in RISC-V Land? (and that has links to further posts going back several years).
Andrew is CEO of Cerebras Systems. They are the company that you've probably heard about that built a chip that is a single die the size the largest square you can get out of an entire 12" wafer. They worked with TSMC to develop special technology so that signals can cross the scribe line between the areas created by repeatedly stepping the reticle (that we would normally call die). He opens Wednesday morning, July 22, with a keynote (going for the longest title award) A Massive Wafer-Scale Supercomputer for Deep Learning Acceleration: A Radically New Paradigm for Deep Learning Acceleration. I have covered this before in HOT CHIPS: The Biggest Chip in the World. However, this keynote promises more information about how the system is programmed and more (that HOT CHIPS post is mostly about the chip design and manufacture).
On Thursday, July 23 at 9:20am is the keynote by Andrea Goldsmith. For her, 5G is over and her keynote is titled New Paradigms for 6G Communications. She will talk about some of the challenges for the future, including new modulation and detection techniques, blind MIMO decoding strategies, machine learning equalization and source-channel encoding, as well as fog-optimization of resource allocation. I've not written about 6G, but my last post about 5G was just a month ago in 5G: Connecting All the Things.
Monday's SKY Talk is from 12:30pm to 1:15pm. So get your lunch and listen to Tony Capell, VP of Industry Architecture and Client Success in IBM's data center business. He will talk about Succeeding with AI Today and Tomorrow. Basically, he plans to talk about the use of AI in your work and your business. So grab your lunch and watch Tony.
Tuesday's SKY Talk (same time) is by Chris Ré of Stanford. His talk is intriguingly titled If You Want to Be Rich, Get a Lot of Money: Theory and Systems for Weak Supervision. His title is a deliberately useless truism, equivalent to the real topic of his talk, that if you want to build a high-quality machine learning product, you need to build a large, high-quality training set. He will talk about how, by using weak supervision and automatic data augmentation policies, it is possible to build training sets more cost-effectively.
Wednesday's SKY Talk (same time) is by Greg Yeric of Arm. He will talk about Design and Manufacturing in 2030. I covered his talk at Arm TechCon last year in my post Arm TechCon: A Look at 2020 and 2030, It may sound like he's giving the same talk, but his mini-keynote at TechCon was very time-constrained, and now he has 45 minutes. He will speculate about how design for manufacturing (DFM) became design technology co-optimization (DTCO) and will need to continue to strengthen if we are going to be able to take advantage of disruptive technologies over the next decade.
Serge Leef is one of the program managers at DARPA. His Tech Talk will be from 2:00pm to 2:45pm on Monday. His area is open-source EDA software...not just in academia but what it takes to use for real designs. The DoD has a problem that their production volumes are really low so that their semiconductor costs are completely dominated by the cost of design and design tools. One particular program they fund that I have written about is OpenROAD: Open-Source EDA from RTL to GDSII.
At 11:00am on Wednesday, Amir Salek will talk about Using Machine Learning to Accelerate Chip Development. Google has done work on using placement (in the EDA sense) as a reinforcement learning problem. Innovus also makes use of machine-learning to produce better results more quickly.
Not officially a SKY Talk or a Tech Talk, but at 11:00am on Tuesday, Jay Vleeschhouwer will give his annual view of The State of EDA: The View from Wall Street. I covered his presentation last year in my post DAC: The View from Wall Street.
Cadence Academic Network is exclusively sponsoring two student activities at DAC this year: Design Automation Summer School and the PhD forum. More than 410+ students from around the world have registered, in comparison to 40-50 at the in-person event. There are two tracks in the summer school – Technical development and Professional development. The technical track will be a small project using SystemC with a Stratus flow where the students can synthesize a small "chip" using the Cadence GPDK, and the professional development track will include a panel discussion by our recruiters where students will be able to ask any question they have always wanted to ask a recruiter. The PhD forum will be a virtual poster session with breakout rooms for students to talk to attendees.
Everything is on the DAC website.
As always, there is a big matrix of the whole of DAC that you might not know exists and might not discover. It shows all the events laid out each day, and you can click on any event to get full details. Don't rely on this static image since I just took a screenshot to give you an idea of what it looks like, but here's one day:
I will cover what we are doing at DAC...including the time slot when I will be at our Expert Bar and so you can drop by (virtually, of course) and meet me or ask me questions.
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