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I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the same glory as the more high profile parts of the EDA flow such as synthesis, or place & route, or signoff.
Over the years, how we do test has been through a number of eras:
Modus times: Cadence's Modus DFT Software addresses these issues by integrating test with physical design. Instead of the gates that create the compressor/decompressor logic being grouped in the center of the chip, they are forced to be spread around the chip in a way that is efficient from a layout point of view. To increase compression ratios further, what we call elastic compression, sequential elements are added to the codec too, to make it possible to preserve and values between vectors. For more details on Modus, see my post Modus Test Solution—Tests Great, Less Filling.
I opened by saying that test generally doesn't get the same respect as "sexier" areas of EDA. But that is not correct this year. The Kaufman Award for 2019 went to Tom Williams, who is one of the fathers of scan test, the way all digital chips are tested today. I wrote two posts about him, one, when I interviewed him just after the award, was announced (see my post Figure-Skating Champion Wins Kaufman Award), and once after the award ceremonies (see my post Kaufman Award Dinner: The Tom Williams Story).
One of the people who worked with Tom over his career, starting in early days at IBM, was Rohit Kapur. During the award dinner, he talked about working on compression with Tom. A couple of weeks ago, he talked with me.
I interviewed him for a video on what he sees as the current issues with test, and how Modus is addressing them.
There is lots, including more videos, on the Modus DFT Software Solution product page.
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