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Hyperscale data centers are bandwidth-hungry (and power-averse) and so the most important interface right now is 112G SerDes. You probably already know that this is a high-performance serial interface that runs at 112 Gb/s. The interface uses PAM4 signaling, meaning that two bits of data are transmitted on each clock cycle. You can clearly see the three eyes separating the four signals in the image below.
Cadence unveiled the 112G-LR (long reach) IP in TSMC N5 this May and the silicon results are available. This is our third version of 112G SerDes IP, and compared to the second version it offers 25% power savings, 40% area reduction, and better design margins.
I have written a couple of posts about 112G SerDes. The first post below is mostly about signal integrity, but it contains a more detailed description of PAM4 signaling. The second post is about the earlier 5nm version of the Cadence 112G SerDes IP.
A new silicon demo video was recently released. It demonstrates the transmitter performance at 106.25Gbps Ethernet data rate as well as the long-reach link performance at 106.25Gbps with a superior BER of 9.6E-8.
Cadence recently taped out its latest version of this IP supporting 112G-ELR (extended long reach). The 112G-LR version has been "extended" to support ELR (extended long reach) in advanced nodes. 112G PAM4 is made possible with sophisticated DSP processing to comply with standards-based connectivity. However, signal integrity at the system level is very important since there are potentially impairments from package, PCB, connectors, and other issues which might cause an increased bit error rate (BER) in a production system.
The diagram above shows typical uses of 112G-ELR SerDes and where reflection issues might occur at connectors, package boundaries, and so on. The diagram above shows the signal connecting to optical fiber but this could potentially be copper, which is still more demanding since the signal does not terminate in the optical interface but has to make its way through cables and connectors to terminate on an SoC on the other board. The extended long reach PHY provides an additional performance margin to handle these demanding environments by incorporating reflection cancellation and enhanced DSP processing. These include incremental changes with more FFE taps as well as floating FFE taps to cancel reflections in the right spots. This provides 1-2 orders of magnitude improvement in BER on high-loss and reflective channels.
In fact, the diagram above is a simplification of many systems providing high-capacity routing, which may have a chip with dozens of 112G SerDes interfaces, which adds more complexity to the board and especially package designs. As Brad Brim told me when I interviewed him when he retired (see my post Brad Brim and the History of Signal Integrity), "we used to call these frequencies microwave". Light travels a foot in a nanosecond, and with two bits alongside each other per clock cycle there are about 60B cycles per second, so a cycle is only about a tenth of an inch long.
The new version of the 112G IP with support for ELR improves system robustness and lowers the risks to production.
Customers are already adopting it in 7nm, 6nm, and 5nm.
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