Get email delivery of the Cadence blog featured here
Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosystem around each of the new processes. There were then three keynotes by the leaders of the three big EDA companies. That was followed by more technical presentations on various areas. I will cover some of the Cadence ones in blog posts in the new week or two.
The day before had been the virtual Technology Symposium. I covered that in two blog posts:
TSMC Technology Symposium: All the Processes, All the FabsTSMC: Specialty Processes and Specialty Packaging
I'm going to assume that you have read those posts, in particular, that you already know the process roadmap.
Cliff opened his keynote with an overview of the markets that TSMC and its OIP Ecosystem are focused on. See the diagram below.
All of these markets require some tweaking to processes, libraries, qualification (for automotive anyway), and a different portfolio of third-party IP from companies like Cadence.
TSMC uses the Arm Cortex-A72 as a test vehicle to see what performance is achieved on a "real" design. The graph above shows how the latest processes fit together. N7 and N5 are in production. N3 was announced in the Technology Symposium
N6 is a sort of shrink of N7, making use of more EUV. This reduces cost and allows for tighter pitches if a design is redone. Alternatively, an N7 design can simply run in N6 and have lower cost and higher yield due to the reduced number of process steps from EUV versus multi-patterning. I discussed all these processes in my post about the Technology Symposium, or you can read them off the chart.
Automotive has its own process roadmap, in the sense that not all processes receive the extra work needed to make a process qualified for automotive designs. The first automotive process was 16FFC. TSMC’s N5 Automotive Design Enablement Platform will be ready in 2022, following up on the N7 platform launched earlier this year. Automotive grade requires additional qualification, extended temperature range, aging models, and so on. There is also additional tracking of designs through the fab so that there is always traceability back to how automotive chips were manufactured. N7 is more complex than N16 since there is more significant hot-carrier injection, and a new statistical signoff that takes heating and stricter EM limits into account.
Ultra Low Voltage design in the N12e process requires some additional features in design tools, as you can see from the above table. Cadence will implement all of these, of course.
3DFabric is the new name under which TSMC has grouped all of their advanced packaging, CoWoS, InFO, and SoIC (also known as "chip stacking"). Cliff went into some detail on the flows associated with some of these flows, but there are so many it is too much detail to cover here.
This table summarizes the state of readiness of the three main advanced 3D packaging technologies that TSMC has available.
Cliff's summary was:
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.