Way back in April 2016, I wrote a post about Cadence IP for PCI Express (PCIe) Gen4 where we demonstrated compliance with Mellanox (now part of NVIDIA). As Mellanox's Gilad Shainer said to me when I talked to him back then:

interoperability is the only way to prove standards compliance.

That was certainly true two years ago since the standard had not been completed. Cadence has attended all the Gen4 FYI testing from the time it got started in August 2017, and our PCIe Gen4 IP has interoperated with over a dozen other vendors without any issues.

Certification

But now the standard is complete. Actually, it has been complete since October 2017, but only this summer was there official compliance testing and certification. At the recent First Official PCIe Gen4 Compliance Testing at the PCI-SIG Compliance Workshop in Burlingame, we brought in our hardware and got it formally certified. We are now on the official list (see below).

The standards processes move slowly compared to the market requirements, so this way of operating, building IP and test chips from the early spec, is increasingly normal. For example, we did something similar with the DDR5 standard, working with Micron, which I wrote about in my post DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s. The DDR5 standard was expected to be finalized late 2018 but now it is looking like 2020.

PCIe (which stands for Peripheral Component Interconnect Express) is derived from predecessors such as PCI and PCI-X. It implements serial point-to-point interconnect to allow communication between two devices. In particular, It is the common motherboard interface for connecting up graphics cards, hard drives, SSDs, and network interfaces.

PCIe Gen4 runs up to 16 lanes at 16GT/s (so 16Gb/s per serial link). This is double the perforrmance of PCI Gen3 with up to 16 lanes running at 8Gbps. However, in practice, people don't run that many PCIe Gen3 lanes, if they need more bandwidth then they step up to PCIe Gen 4. The next generation will be PCI Gen5 and will run at 32GT/s and PCIe Gen6 will run at 64GT/s. Since Cadence already has a 112Gb/s SerDes running, there shouldn't be any major issues meeting the standard (see my post The World's First Working 7nm 112G Long Reach SerDes Silicon for the details on that).

The table summarizes the performances and bandwidth for the different generations. There is a 20% overhead on Gen1 and Gen2 due to 8b/10b encoding, and about 1.5% overhead for the higher speed generations due to 128b/120b encoding. These extra bits (and some scrambling) are done to ensure there are sufficient transitions to keep the receiver clock synchronized. Preliminary standards for both Gen5 and Gen6 have already been announced, which is a much faster timeline between generations than used to be the case. PCIe Gen6 is planned for 2021 and will use PAM-4 encoding (two bits per clock) and forward error correction (versus NRZ used at the lower data rates), like the 112G SerDes I already mentioned.

PCIe Gen4 designs are being done with Cadence IP in 16/12nm and 7nm. Cadence has a couple of dozen customers doing designs with the Cadence IP. In data center and enterprise networking, the designs are mostly in 7nm. In automotive, they are mostly in 16nm. The designs are at varying stages from just being designed-in to sampling products. Despite the certification just being a few weeks ago, for us this is already a mature product with existing customer successes.

Plus PCIe Gen3 is not dead, new designs are still being done in IoT and consumer applications that don't need the higher performance and the associated costs.

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page. There is also a portfolio of Verification IP (VIP) for PCIe Gen4 with details on the PCI Express VIP page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

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