RISC-V Summit 2022

The RISC-V Summit took place in December. It was in person and virtual. Clearly, in the world of processors, RISC-V is the most important development of the decade. It has already taken over academia completely. It has a huge footprint in the embedded space. And this year, for the first time, many high-end processors that have been in stealth development for several years were on display.

I first came across RISC-V at EDPS in 2016, and then again later that same year when Krste Asanovic presented it at DAC. I recently wrote a sort of tutorial on RISC-V as a prelude to the summit. So you can read my posts:

• RISC-V—Instruction Sets Want to Be Free
• RISC-V Tutorial

If you don't know much about RISC-V, I recommend you read the tutorial before reading the rest of this post.

Calista Redmond

The summit opened with a keynote by Calista Redmond, the CEO of RISC-V International.

I actually met her in her previous gig, doing a similar job for the OpenPower Consortium, getting more people to use the open version of the PowerPC architecture. But the PowerPC architecture was originally created by IBM, Apple, and Motorola, and today only IBM still uses it (for high-end servers), which is going in the wrong direction.

But RISC-V is booming.

RISC-V membership grew 26% this year and now has over 3,180 members (I say "over" since Calista said two more people had joined just that morning, so her slide was already out of date).

The three big points Calista made (and which Krste would return to in his "state of the union" keynote the following day) were:

• RISC-V is inevitable
• RISC-V enables the best processors
• RISC-V is rapidly building the strongest ecosystem

There are processors available now at every performance level, from low to ludicrous, meaning from embedded microcontrollers up to supercomputers. With investment spread over a lot of companies, not just a single company, this is driving adoption and the entire ecosystem (not just chips, but a lot of software).

Manju Varma

Next up was Manju Varma of Qualcomm. Qualcomm first used RISC-V in 2019 when they needed a customizable microcontroller for the Snapdragon 865. Qualcomm actually pre-announced this (sort of) at the 2018 RISC-V Summit (see my post RISC-V: Real Products in Volume) where Qualcomm ended its presentation with:

I end with an announcement: Qualcomm will be shipping RISC-V in a high-volume product in 2019.

Qualcomm has not made a lot of noise about it, but Manju revealed the number:

Yes, Qualcomm has shipped closing in on a billion RISC-V cores in its products.

Lip-Bu Tan

The final keynote was Lip-Bu Tan, who needs no introduction around here, although he was talking with his investment hat on, rather than his Executive Chair of the Board of Cadence hat. Lip-Bu is one of the few VCs who invests in semiconductor startups. He complains that when he talks to other VCs about these investments, they walk away. But he has been very successful:

I've invested in 85 semiconductor companies.  So far I've had 19 IPOs, and 26 trade sales.

Lip-Bu talked about his Arm investments first (yes, he was the guy who talked about Arm at a RISC-V conference).

Annapurna, I sold it to Amazon. NUVIA, I sold it to Qualcomm

Then he moved onto his RISC-V investments:

• SiFive
• Ventana
• RiVos
• Akena

Except for Akena, the other three all had multiple presentations at the summit.

 

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