The First Decade of RISC-V: A Worldwide Phenomenon

A couple of weeks ago was the RISC-V Global Forum. Earlier in the week, I wrote about RISC-V State of the Universe, mostly covering Krste's keynote that was at 8:00am—that is to say, in the middle of the conference! Today, I will cover Dave Patterson on The First Decade of RISC-V: A Worldwide Phenomenon. Dave, as you probably know, developed the original RISC (now known as RISC-I) and another three generations after that. But after RISC-II, he didn't keep calling the series RISC-III and RISC-IV, despite having coined the phrase RISC for Reduced Instruction Set Computer. RISC-V returns to the original naming (I assume you know that the "V" is a Roman numeral and so is pronounced "five").

For more background on Dave, see my previous posts:

• Hennessy and Patterson Receive the 2018 Turing Award
• Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness
• Fifty Years of Computer Architecture: The First 20 Years and The Last 30 Years

If you've never seen Dave talk about how nobody would publish his paper on how CISC was never going to work for SoCs, and so he invented RISC, then I recommend reading the 50 Years of Computer Architecture posts above, which also makes up a large part of his (along with Hennessy's) Turing Award acceptance. RISC has been so successful that since the RISC-1 there has never been a single new complex instruction set. Plus, if you know how a modern out-of-order CISC processor (such as IBM z-series or x86) works under the hood, you already know that the complex instructions are decoded into RISC instructions and then handled with the same basic RISC approach.

2010

RISC-V had its roots in two programs at Berkeley looking at computer architecture, called Par Lab (the Parallel Computing Laboratory) and RAMP (Research Accelerator for Multiple Processors). They considered SPARC but 32-bit was open however 64-bit was not. Next choice, OpenRISC but again it was only 32-bit. Arm and x86 were impractical due to licensing. So they decided to create their own instruction set. The email that kicked off the project was dated May 18, 2010, so that is the birthday of RISC-V, although it didn't get that name until six weeks later.

2011

By 2011, they had the 1.0 version of the manual. As you can see, it is dated almost exactly a year later. Of course, this enabled outsiders to discover it, including Arvind at MIT who had worked with Krste when Krste had been there.

2013

In 2013, Nikhil of Bluespec learned of RISC-V from Arvind and implemented the ISA in Bluespec (which took two to three days of work since it is only 40 instructions). He then met with IIT Madras who had a project called Shatki. A couple of months later on July 22, they switched that from Power architecture to RISC-V (slightly embarrassingly, Shatki is Sanskrit for "power").

2014

In winter/spring 2014, IIT Madras contacted the team at Berkeley:

IIT Madras: Stop making changes to the instruction set
Berkeley: Why do you care?
IIT Madras: We're implementing RISC-V

That was the lightbulb moment when they realized there was a demand for a worldwide open ISA...and they had one.

First we had to finish the version 2 of the ISA manual...and then we went to work on making it popular.

So later that year, in combination with Microprocessor Report, they produced Instruction Sets Want to Be Free: The Case for RISC-V. In an attempt to get a sort of repeat of the CISC vs RISC debate going, they also had Arm present the other side in The Case for Licensed Instruction Sets.

The team from Berkely also went to that year's HOT CHIPS to both promote RISC-V and recruit attendees for the first workshop planned for early the following year. Later that year, two things happened that only came to light recently. Benini of ETH Zurich read Instruction Sets Want to Be Free and switched Pulpino from OpenRisc to RISC-V. Mke Aaronson of Rumble Technologies read it and switched an FPGA-based camera product from MIPS to RISC-V in three weeks. When it shipped, this was the first-ever commercial product to use RISC-V.

2015

The first workshop took place in January in Monterey with about 50 people from 20 companies. The second took place in June with about 150 people from 40 companies. A week later, the first RISC-V startup was founded by the creators of the RISC-V ISA (SiFive). Again, "unknown to us", at the end of that year, NVIDIA decided that the next version of their control processor (that ships in every GPU) would use RISC-V instead of their proprietary instruction set.

2016

At the Shanghai RISC-V workshop, Andes switches from a proprietary ISA to RISC-V and NVIDIA announced publicly the decision that they had made.

2017

The following year, "textbooks switch from MIPS ISA to RISC-V". You can't really read it in the book above, but Dave is the co-author of the book, the standard textbook on computer architecture (and the standard graduate-level book, Computer Architecture: A Quantitative Approach). DARPA announced that their security program SSITH will be based on RISC-V, and Microchip added a RISC-V option as a soft core in their FPGAs.

2018

2018 sees a growing interest in RISC-V. At the December workshop in Milpitas (at the old SanDisk offices since Western Digital had acquired them), Martin Fink, CTO of Western Digital, announced that they would switch all their cores to RISC-V. Since they ship over a billion cores per year, this was significant. He later said that he wanted to have the same impact as IBM when it announced they had invested $1B in Linux.

The European Processor Initiative (EPI) selected RISC-V. Look for a Breakfast Bytes post on this project in the next week or two.

Motivations for RISC-V

Some of this was planned. Of course, it was free and open since they created the ISA to share with other academics. One thing that RISC-V enables for startup companies is that they can pick the architecture and then pick the vendor. The ISA goes from tiny computers to large ones:

One novelty is 128-bit. Tthe only thing you can't recover from in computer architecture is not having enough address bits. Warehouse-scale computing is already up to the 50th bit, so it will get to 64, and the next power of 2 is 128.

Another unexpected one was the interest in nation states to have secure processors where they could see everything and there were no secrets in the cores.

The Center of the RISC-V Universe

Dave then ran through, somewhat tongue-in-cheek, reasons that the center of the RISC-V universe is the US, or Europe, or Asia. But the reality is that it is worldwide. As you can see, there are over 600 members in 47 countries with over 2,000 individuals participating in extension standardization efforts.

RIOS

Dave's latest project is RIOS, the RISC-V International Open Source Laboratory. it is built on top of TBSI, the Tsinghua University Berkeley joint venture located in Shenzhen since 2014. Dave is the director (in the US).

To drive work, they are using the PicoRio, which is a small open-source computer based on RISC-V (so like Raspberry Pi but with RISC-V instead of Arm). Plus it has a cute logo already.

Dave's Vision

Videos

All the presentations from the Global Forum are now available on the RISC-V YouTube Channel.

There were plans for a 10th-year anniversary celebration before COVID-19 made that impossible. So instead they made a series of 10-year videos instead (also all on the YouTube channel linked above).

Here are a couple, one a three-minute overview, and a second longer one that is more similar to this blog post and digs into the history.

RISC-V 10th Anniversary: RISC-V In More Depth: Exploring Its First 24 Milestones (39 minutes):

The name of the videographer who made all the videos? Grace Patterson. That last name is not a coincidence, she is Dave's grandaughter.

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