TSMC: Mobile, HPC, IoT, Automotive...and Packaging

This is the third post about the TSMC Technology Symposium that was held on May 1st. The first two are TSMC Technology Symposium 2018 and TSMC's Fab Plans and More. In the afternoon, there were four presentations:

• Doug Yu on Advanced Packaging Technology
• BJ Woo on Technologies for Mobile and HPC
• Kevin Zhang on Technologies for IoT
• Chung Ming Lin on Technologies for Automotive

Since the base technologies for everything are the processes discussed in the morning sessions (and in my earlier two blog posts), there was a fair bit of repetition, although there was more detail presented in these afternoon sessions. Also, the packaging session was in the middle, but I decided to pull it up to the front since the three other presentations cover the four applications areas on which TSMC is focused: Mobile, HPC, IoT and Automotive.

Doug Yu: Packaging

Doug started off by saying that "most of my presentation you won't hear anywhere else." He talked about what TSMC groups together under the term WLSI or Wafer Level System Integration technologies, and outlined his presentation as:

• Bumping and WLCSP advances (WLCSP is Wafer Level Chip Scale Package)
• InFO
• CoWoS
• SoIC (System on Integrated Chips)

Bumping and chip-package interaction: TSMC needs to ensure concurrent deployment of advanced silicon and robust flip-chip package solution. They qualified on 16nm (including automotive), 12FFC, N10 and N7. The target is to qual N5 in 3Q 2019.

WLCSP: TSMC just completed qual of 1.0, version 2 is planned but they are adding a 1.0+ in between to get a 0.3mm ball pitch for BGA and expanding to cover 16/12nm products.

5G is driving the InFO packaging technologies.

InFO_PoP has a dual die in the same package with DRAM on top of the mobile application processor. For 5G, with its split frequencies, they need to use MUST (MUlti-layer STacking) since th 6GHz and the mmWave radios need different manufacturing technologies. InFO_AIP (antenna in package) goes further and requires both a patch antenna and a dipole antenna.

MUST is second generation InFO with RDL (redistribution layers, aka routing) supporting a 40um pad pitch. This is qualified for 6mmx5mmx0.6mm package which has better performance compared to the old hybrid approach with the memory wire-bonded above the flip-chip AP underneath. It is 0.8X the thickness, 0.9X the area, and 1.1X the performance.

HPC is driving the interposer based technology CoWoS. The interposers are getting bigger (1 reticle is 830mm²). They are working on 1.5X and 1.7X reticle sizes (2X by the start of next year). More and more customers are using CoWoS (names Doug mentioned were AMD, NVIDIA, Xilinx, Mediatek, eSilicon, Broadcom, HP Enterprise).

InFO_oS is technology for packaging two chips side by side, with 2um chip-to-chip interconnect. There is less than 70m gap between the chips. 130um c4 bump pitch, will go down to 100um. InFO_MS is basically the same but with HBM (high bandwidth memory) alongside the SoC. Qual is by end of 2018. It is a bigger challenge with HBM since more moulding compound is involved.

Doug introduced SoIC which is "innovative stacking of multi-chips with very fine <10nm chip on wafer bonding process". There is a bumpless bond structure and thus minimal parasitic for better performance. I believe that the wafer-on-wafer WoW technology for which Cadence has a complete tool flow certified is a subset of this technology when two die the same size are involved.

Doug showed a cross-section. They have achieved 95% yield on 4.8M CoW bonds. It has passed early reliability assessment. 

TSMC's aim in this area is to grow from a plain IC foundry to a system-wafer-level foundry.

BJ Woo: Mobile and HPC

Market trends are that data traffic is growing at 50% CAGR all the way through 2020, driven by 5G, social media, 4K streaming, live streaming, VR etc. AI and 5G further drive innovation.

Mobile is seeing a 10X modem speed increase from 1 to 10Gbps. AI engines are increasing by 3X. CPU is inceasing by 1.5X from Specint 25 to 38. GPU is increasing by 2X from 650 GFLOPS to 1300 GFLOPS. Transistor counts from 5B to 10B...but power budgets are unchanged.

HPC base stations are going from 10Gbps for 4G to 100Gbps for 5G. Cloud switches are going from 12Tbps to 25Tbps. AI accelerators are increasing by 3-5X with their memory bandwidth doubling. 20B transistor counts are going to 80B...but once again power budgets are unchanged (at 300W).

The high-end process roadmap goes 16FF+, 16FFC, N10, N7, N7+, N5.

The mainstream process roadmap goes 28HPC+, 16FFC, 12FFC, and eventually beyond.

High end: N5, and N10/N7/N7+, for mainstream, 16FF/12FFC. Covers both premium and mid to low end.

N7 PPA (versus 16) is 3X density improvement, 35% speed gain, 65% power reduction. The N7 HPC track provides a further 13+% speed gain over N7 mobile. 

BJ gave some manufacturing status. N7 is the fastest ramp ever, with lower defect density faster (yield learning) resulting in a steeper ramp than 10. It is going "much better than planned" with yield and qual status ahead of where N10 was in the same period. N7 is in volume production in both Fab 12 and Fab 15.

According to BJ, some nodes at TSMC come and go, and othes are much longer lasting:

N7 will be another strong node at TSMC. We intend to make 7nm a very long lived node like 28nm and 16nm

N7+ is the second generation of N7 with EUV on selected layers. They can leverage production learning on the healty baseline of N7. There is much tighter distribution on N7+ than N7, especially via resistance (fewer very high resistance vias). As a result, EUV doesn't just result in faster cycle time but also higher yield and a better process window. Compared to N7, it is 20% denser, 10% less power. They are achieving an increase of double digit die per wafer over N7, and of course that yield increase is biggest with the largest die size. It uses the same equipment set as N7.

Porting from N7 to N7+ requires some layout changes, which can be automated, and a re-K (re-characterization). TSMC have already implemented this on their own test vehicles and are now working with customers. N7+ is better value and faster time to market (fewer masks). Product tapeouts are expected in Q2 and production in 2019. N7+ also has a dedicated HPC track, with about 10% more speed or 20% less power. It also has denser standard cells, ultra low voltage technology (ULVT) transistor. There are 1-fin cells which enables dynamic power reduction on non-critical timing paths, with a power saving of up to 10% just by switching to use these cells off the critical path. There is a new SHDIMM for enhanced MIM capacitance that doubles the MiM-cap density for HPC performance enhancement, with 2X the fF/um², resulting in a 3-5% speed gain for N7+.

Next BJ went on to N5. This is a full-fledged EUV process. It will be ready in 1H 2019 for risk production. 

The basic N5 has 15% better speed than N7, or 30% lower power. The logic density is up 1.8X for digital, 1.3X for analog. Adding the eLVT devices increases speed gain to 25%. Development is progressing well with double-digit yield on SRAM repeatedly, very clear eyes at nominal VDD and even with VDD + and - 20%.

BJ went back up a few nodes for the mainstream to talk about 16FFC and 12FFC (its optical shrink). She described them as "cost-effective technologies for your mainstream products."  Looking at these processes, if 16FF+ is 1X, then 16FFC is 0.98X speed, 0.9X power, 0.96X area. 12FFC is 1.1X speed, 0.8X power and 0.86X area. 12FFC uses 6 track snandard cells for 10% speed or 20% power gain, and 20% better logic density. 

One challenge with FinFETs is to use the processes to migrate consumer products, many of which are using 5V. BJ said she was "proud to present to you our FinFET 5V LDMOS solutions" which have a 30% area reduction compared to the conventional cascade structures. This allows consumer products to migrate from 28 to 16/12.

There is a new vertical MOM (VMOM) with gate-MOSCAP. It produces a 1mW saving per 100mm² of die (assuming 20% decap in std cells) with negligible leakage. 

There is strong customer adoption of 16FFC and 12FFC with over 220 customer product tapeouts. 12FFC will ramp to over 50% of 16 FFC by end of 2019 (I think that this meant 12FFC will be over half the combined 16/12FFC volume).

TSMC is rearchitecting mobile RF for 5G due to the very wide spectral range from sub-6GHz to mmWave. There are different technical ramifications at each end of the spectrum. They have the industry-leading RF SOI for 5G, with over 170 tapeouts and 100K wafers shipped. BJ finished by showing a complicated RF roadmap which showed how all these 3 pieces fit together, but way to complicated for me to attempt to record. But the 3 components are sub-6GHz, mmWave, and RF front-end SOI.

Kevin Zhang: IoT

IoT is a growth driver for TSMC for ultra-low power technology, RF enhancement, MRAM, RRAM.

IoT numbers are always big, and Kevin's were:

• wearables 800Mu (million units), 24% of market
• smart home 2.5Bu, 33% of market
• smart city, 1.3Bu, 15% of market
• industrial, 1.6Bu, 31% of market

Just like BJ had roadmaps for high-end and mainstream, Kevin had the same.

For high end IoT, the roadmap is 28LP, 28HPC+, 28HPC_ ULL, 22ULP, 12FFC, 7nm

For mainstream (low leakage edge devices) it is 55ULP, 40ULP, 40ULP low Vdd, 20ULL, 12FFC_ULL

There is a third roadmap for the many devices that also require non-volatile memory, starting from 40ULP with eNVM (floating gate eFlash) but switching to MRAM and RRAM, all the way down to 12FFC_ULL_MRAM.

Kevin said something that I think we all knew but I don't remember hearing said explicitly before: 28nm is TSMC's biggest volume runner to date over all processes (he said that maybe one day 7nm will overtake it, but not for some time for sure).

22ULP/ULL is based on 28HPC+ with a basic optical shrink resulting in 10% speed increase or 20% power decrease, and 10% better area (it's a 10% shrink). Also adds RF and better AMS. 22ULL also adds the eHVT triple-gate-oxide transistor, ultra-low-leakage SRAM, and eMRAM/RRAM. There is a 0.6V enablement plan which starts with getting SPICE to work down to 0.54V and then a library recharacterization. Also, an SRAM with 0.8V array and 0.6V periphery. The voltage is so close to the threshold it requires a new advanced signoff methodology.

IoT Memory

Embedded non-volatile memory is important for IoT for things like holding microcode and security keys. However, at 28nm, the eNVM solution is 18 masks and so is cost-prohibitive for IoT. However, the new memory technologies are "here to rescue us". 

MRAM works by changing the resistance of the memory cell by altering the magntic dipole direction, based on magntic tunnel junctions (MTJ).  “We have spent our whole career moving electrons from A to B. This is the first time we are not moving electrons, we are moving the spin, which is how you distinguish 1 and 0." MRAM is a general eFlash replacement. It has excellent endurance and the memory can be accessed frequently like SRAM.

RRAM works by changing the resistance with a conductive filament that is connected or disconnected. It is a cost-sensitive memory for IoT and consumer.

Both MRAM and RRAM are built in the BEOL, with no need to touch the transistor, so it is easy to move across technology nodes. It can just be added to the metal 4 stack without changing anything else.

What is the manufacturing status? 28MRAM 10Mb achieves >95% yield, almost enough for what is needed for HVM (before adding repair). 22MRAM will be ready for risk production in December 2018. It is making excellent progress with a write time 3X faster than eFlash, >1M cycles endurance, 10 years at 125°C after 1M cycles, no data loss after 260°C..

There is strong customer adoption with over 150 tapeouts planned and a steep ramp. 

Cheng-Ming Lin: Automotive

You don't need me to tell you what is driving automotive. TSMC's automotive approach has been centered around 16FFC and the second automotive-focused node will be N7. 16FFC is fully ready, with the first devices in production and more tapeouts planned.

The ecosystem will be moved to N7 and will be ready by Q2 2019. It has passed process reliability assessment to Grade-1.

Since Cheng-Ming went at the end of the day, some of the details of the processes and schedules duplicated information from earlier, so I won't repeat it all.

Some specialized automotive technologies:

• MRAM for automotive is undergoing feasibility checks by 2H 2018, so "hopefully I'll have good news to share with you this time next year."
• CIS (CMOS image sensor, for video or Lidar). The key things are to handle all conditions and to use a global shutter to minimize distortion. The CIS is stacked on top with logic on bottom, and pixel level stacking using WoW (the only other mention of the technology since Cliff Hou in the morning). This means feeding each pixel from the image sensor to the image processor directly.
• BCD but industry is moving to 48V so need higher voltage integration of BCD and MCU to keep costs down
• GaN power devices for automotive by 2019

Cheng-Ming wrapped up with some other things that automotive companies care about with their focus on reliability and 15-20 year lifetimes. First, business continuity. TSMC never take a fab out of production, so you will be able to get production for a long time. Second, TSMC has the best score among foundries for risk management (least likely to go out of business). And finally, they do about 50 audits per year (199 from 2010 to 2017).

It is a fast-growing business. Automotive has grown at a CAGR of 35+% over the last few years, with 50% last year.

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