UCIe PHY and Controller—To Die For

UCIe is the Universal Chiplet Interconnect Express, a type of die-to-die (d2d) serial interconnect. This was announced in March, earlier this year, and I wrote about it at the time in my post Universal Chiplet Interconnect Express (UCIe). I happened to run into Wendy Wu in the parking lot recently (rarer than it may sound since people are working from home most of the time still). She told me that she's never seen such interest in an interface before.

Of course, the basic idea of putting more than one die in a package, often called chiplets, is hot right now. This approach also goes under the name system-in-package or SiP. I have written about this several times over recent years. See my posts:

• ERI: CHIPS and Chiplets
• System in Package, Why Now? and System in Package, Why Now? Part 2
• HOT CHIPS: Chipletifying Designs
• Let’s Talk About Chiplets, Baby
• John Park's Webinar on Chiplets
• TSMC's 3DFabric
• HOT CHIPS: Two Big Beasts covering Intel's Ponte Vecchio, the most advanced SiP to date

Until now, apart from HBM stacks, there has been no standardization of how chiplets should communicate. As a result, almost all SiPs have been built up using die from a single company. See the last link in the above list to read about Ponte Vecchio. This contains 47 chiplets (that Intel calls tiles) manufactured on five different process nodes. But, apart from the HBM, all designed by Intel, I think.

The aim of UCIe is to make it more feasible to build SiPs using die from more than one manufacturer, not necessarily designed from the beginning to be part of a single (or small set) of specific systems. In the longer run, it is possible that a chiplet marketplace of some sort might come into existence. Even if it does, I think it will take years. The challenges are more about business models than about technology, at least once everyone is using UCIe.

In my earlier post on the UCIe standard, I said:

But I don't think I'm going out on a limb to say we will be adapting our D2D interconnect to follow the standard.

Well, that turned out to be a correct prediction!

UCIe PHY

The Cadence UCIe PHY is a high-bandwidth, low-power and low-latency die-to-die (D2D) solution that enables multi-die system in package integration for high-performance compute, AI/ML, 5G, automotive, and networking applications. The UCIe physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe architecture supports multiple standard protocols such as PCIe, CXL, and streaming raw mode.

The diagram above shows how the various blocks communicate with the signals defined by the UCIe standard for both the standard package module (2D) and advanced package module (2.5D).

Features of the PHY

• Supports up to 16Gbps per pin including 4/8/12Gbps
• SerDes and DDR architecture
• Forwarded clock, track, and valid pins
• Sideband messaging for link training and parameter exchange
• KGD (known good die) testing capability
• Redundant lane repair (advanced)
• Width degradation (standard)
• Lane reversal
• 2-25mm wide range channel reach
• Low raw BER 1e-27

UCIe Controller

The Cadence UCIe Controller is a high-bandwidth, low-power, and low-latency die-to-die solution that enables multi-die SoCs for high-performance compute, AI/ML, 5G, automotive, and networking applications. The UCIe controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe architecture supports multiple standard protocols such as PCIe, CXL, and streaming raw mode.

Features of the Controller

• Lowest latency controller for data-intensive die-to-die applications
• Supports single and multiple PHY modules
• PCIe, CXL, and streaming protocols
• CRC and retry mechanism
• Sideband messaging for link training and parameter exchange
• Link State Management
• Parameter Negotiation

Putting it All Together

Learn More

See the Product Page for UCIe PHY and Controller.

 

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