Universal Chiplet Interconnect Express (UCIe)

Recently, Intel, AMD, Arm, the two leading-edge foundries, Google Cloud, Meta, Qualcomm, and ASE announced that they are forming a new open standard for chiplet interconnect, named Universal Chiplet Interconnect Express, or UCIe.

One of the big trends of the last few years has been the increasing use of advanced packaging with multiple-die as a way of building silicon-based systems, often called Systems-in-Package or SiPs. There are no major technical challenges to communicating between chiplets, at least none beyond what we already face communicating between chips on boards. However, without any standards, all SiPs have been built with die from a single company (although often on multiple semiconductor process nodes). The one notable exception is HBM (also HBM2 and HBM3) where JEDEC has been involved with the standardization and manufacturers like Micron has supplied die-stacks for incorporating into these advanced-packaging-based designs.

Earlier on Breakfast Bytes...

I'm not going to cover the motivation for putting multiple die into a package as opposed to building an enormous SoC (if that is even possible). I've written a lot about that before, and I'll link to some of those posts.

For some background and examples of SiPs, see my posts:

• ERI: CHIPS and Chiplets
• System in Package, Why Now? and System in Package, Why Now? Part 2
• HOT CHIPS: Chipletifying Designs
• Let’s Talk About Chiplets, Baby
• John Park's Webinar on Chiplets
• HOT CHIPS: Two Big Beasts covering Intel's Ponte Vecchio, the most advanced SiP to date

and Cadence's foray into die-to-die interconnect:

• Die-to-Die Interconnect: The UltraLink D2D PHY IP

Cadence tools for SiP design:

• System in Package? How to Plan and Build It
• Introducing the Integrity 3D-IC Platform for Multi-Chiplet Design

The UCIe Standard

Standards are most useful when everyone adopts them. To me, the most significant thing about this announcement is the list of companies who are already signed on. Quoting myself from the opening paragraph of this post, the initial list is:

Intel, AMD, Arm, the two leading-edge foundries, Google Cloud, Meta, Qualcomm, and ASE.

It remains to be seen which of these companies actually make standard-compliant bare die available. Arm doesn't built chips, of course, and foundries don't design chips, so it is a little bit of a weird ecosystem. But maybe one day it will be possible to build an SiP with an Intel x86 processor, a Google TPU, and a Qualcomm 5G modem, all in the same package.

IP companies were not invited to the initial announcement, probably because getting the semiconductor and system companies all lined up was already herding enough cats. But I don't think I'm going out on a limb to say we will be adapting our d2d interconnect to follow the standard.

Obviously, the model for UCIe is PCIe (you only need to look at the names). PCIe has allowed a huge number of suppliers to build boards and chips that work successfully together. Clearly, the hope is that a similar level of interoperability between chiplets from different manufacturers is the goal. It remains to be seen what kind of business environment comes into being to support this. At the very least, it should be possible to purchase die from multiple companies, have those companies fabricate them, and have them work together as you assemble them into an advanced multi-die package. Going further, the companies might have an inventory of die available off-the-shelf, so you do not have to wait for them to be fabricated. And even more intriguing, perhaps distributors (or some new sort of companies) might hold die inventory from multiple manufacturers in much the same way as they hold packaged parts today.

A big motivation for doing d2d interconnect is that it can have higher performance and lower power than off-chip connections over a PCB. Indeed, the initial launch promises 20X the performance at 1/20th of the power (see the diagram above from the press release).

As with PCIe (and USB) the initial development of the standard was done by Intel, who have then donated the standard to what will be (or maybe already is) the UCIe Consortium. But the closest standard is actually the Advanced Interconnect Bus (AIB) which was also originally developed by Intel, and then donated to the CHIPS Alliance. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems and is focused on open-source hardware and tools.

But it is clearly not just an Intel standard, as you can see by the list of companies that signed up for the initial announcement. When you get Intel, AMD, and Arm working together, it certainly seems significant. The specification covers both the physical layer (the electrical signaling standards) and the protocol layers above. It also details supported bump pitches, which is an indirect way of specifying which advanced packaging technologies can be used.

The above table gives a deeper dive into the numbers in the initial standard.

There is a white paper available for download Universal Chiplet Interconnect Express (UCIe) Building an Open Chiplet Ecosystem. I'll quote the final paragraph of the summary:

There is a huge demand for an open chiplet ecosystem that will unleash innovations across the compute continuum. UCIe 1.0 offers compelling power-efficient and cost-effective performance. The fact that it is an open standard with a plug-and-play model, modeled after several successful standards, and launched by the right set of industry leaders will ensure its wide-spread adoption. We foresee the next generation of innovations will happen at the chiplet level allowing an ensemble of chiplets offering different capabilities for the customer to choose from that best addresses their application requirements.

Learn More

Here is the press release making the announcement. Here is Anandtech's commentary. And, of course, download the white paper linked-to a couple of paragraphs ago.

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