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Featured

What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

Earlier this week I wrote about the electric vehicle (EV) transition, how it is happening…

Paul McLellan
• 7 min read
ota , Automotive , tier-1 , featured , zonal architecture

The Automotive Electric Vehicle Transition

The only really interesting part of the automotive industry is the electric vehicle…

Paul McLellan
• 8 min read
Automotive , Electrification , featured , ev , nev

Richard Goering, 1952-2023

I have some sad news to report. Richard Goering passed away last month at the age…

Paul McLellan
• 3 min read
featured , Richard Goering , EETimes
Breakfast Bytes

Latest blogs

Fifty Years of Computer Architecture: The First 20 Years

As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture…

• 6 min read
Intel , risc-v , CISC , RISC , ibm 360 , Breakfast Bytes , dave patterson

Dream Chip: A Vision for Your Car

Dream Chip is a company based in Germany just outside Hannover. Martin Zeller presented…

• 4 min read
Automotive , dreamchip , 22fdx , ADAS , GlobalFoundries , Breakfast Bytes , FD-SOI

CDNLive EMEA Zwei

This is the second post about CDNLive EMEA in Munich. Here is the first . If the…

• 9 min read
CDNLive , virtual platform , CDNLive EMEA , Bosch , CDNLive Munich , OrCAD , ARM , arrow , Breakfast Bytes

What's For Breakfast? Video Preview May 22nd to 26th 2017

https://youtu.be/Frsw0YkUF5M Coming from Marienplatz, Munich, Germany (camera…

• less than a min read
open source silicon , computer architecture , risc-v , Heart of Technology , Denali Party , isa , Denali , open source , instruction set architecture

CDNLive EMEA Eins

Every CDNLive has a little bit of a different structure. At CDNLive EMEA in Munich…

• 7 min read
High-Level Synthesis , Automotive , Tom Beckley , CDNLive , CDNLive EMEA , iN7 , JasperGold , HLS , Breakfast Bytes

JasperGold: Stepping up to RTL Signoff

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon…

• 7 min read
Intel , Jasper , JasperGold , Formal verification

The New Tensilica Fusion G6 DSP

Only last week, in Are General-Purpose Microprocessors Over? I wrote about how general…

• 4 min read
fusion G6 , Tensilica , Breakfast Bytes , digital signal processor

FD-SOI State of the Union: There's Supply—Is There Demand?

I went to the annual SOI Silicon Valley Symposium recently. As last year, they had…

• 11 min read
dreamchip , China , NXP , 22fdx , 12fdx , Samsung , handel jones , GlobalFoundries , ARM , ibs , Breakfast Bytes , FD-SOI

RISC-V 6th Workshop 上海

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai…

• 11 min read
computer architecture , risc-v , risc-v foundation , dave patterson

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

• less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

• 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

• 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

• 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

• 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

• 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

• less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

• 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

• 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Vision C5 DSP for Standalone Neural Network Processing

I pointed out recently that although La La Land is a romance, the movie opens with…

• 6 min read
DSP , Vision C5 , embedded vision , Embedded Vision Alliance , Tensilica , semiconductor IP , embedded vision conference , Breakfast Bytes

Growth Comes from Solving New Problems—ESD Alliance CEO Panel

First, some sad news. Bob Gardner, for many years the executive director of the ESD…

• 12 min read
cadence , EDAC , arm holdings , ARM , synopsys , Breakfast Bytes , esd alliance , Mentor

Microsoft CDNLive Keynote: Cloudy with a Chance of Chips

Traditionally at CDNLive Silicon Valley, the first keynote is given by Lip-Bu Tan…

• 7 min read
microsoft , deep learning , cloud , azure , CDNLive Silicon Valley , Breakfast Bytes

The IRDS Panel at IRPS

Confused by those names? The conference is the International Reliability and Physics…

• 4 min read
irds , ITRS , international roadmap for devices and systems , irps , IEEE , Breakfast Bytes , rebooting computing

"The Safest Train Is One that Never Leaves the Station"

The Sunday and Monday at IRPS are tutorial days, with multiple tracks. On Monday…

• 7 min read
Automotive , functional safety , volkswagen , NVIDIA , sotif , ISO 26262 , Breakfast Bytes

What's For Breakfast? Video Preview May 1st to 5th 2017

https://youtu.be/n1uLybW0__s Coming from Millennium Park, Chicago (camera Jessamine…

• less than a min read
Physical verification , ieee 1800.2 , uvm , Genus , Embedded Vision Summit , pegasus , DRC , CDNLive EMEA , TSMC , via pillar , CDNLive Munich , Tensilica , design rule check , n7 , Innovus , cdnlive München , 7nm , vision processor

The $10 Raspberry Pi Zero W

Roger Thornton of the Raspberry Pi foundation talked about designing their latest…

• 6 min read
Raspberry Pi , raspberry pi zero w , bluetooth , PCB design , WiFi , Breakfast Bytes , Allegro

Software Isn't the S in SDE

System Design Enablement (SDE) is about designing optimal systems, focusing effort…

• 8 min read
SDE , open source , software , gcc , system design enablement , linux , Breakfast Bytes

CCIX Is Pronounced C6

Cache coherency has become a big issue as the architecture inside devices such as…

• 4 min read
GPU , ccix , cache coherency , offload processors , Breakfast Bytes , FPGA

Ricardo's Difficult Idea

Today is an important anniversary. It is part of the explanation of why we design…

• 5 min read
ricardo , unemployment , trade , comparative advantage , david ricardo , Breakfast Bytes , technology
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