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Cadence Education Services have released our latest advanced UVM Training Byte (TB) video on support.cadence.com. This TB covers issues when migrating to UVM-IEEE.
UVM is the dominant testbench methodology for ASIC and IC design. For many years UVM was maintained by the industry standards body Accellera, but in 2017 UVM finally became the IEEE standard 1800.2 (UVM-IEEE). Adoption of UVM-IEEE has been slow, perhaps because it does not add any essential new content, but adoption of the new standard is inevitable, and we are seeing increasing interest in migration. The good news is that this is an easy migration, but the bad news is that a small number of constructs and coding styles in your testbench will break in UVM-IEEE. This TB identifies the top five common issues when migrating to UVM-IEEE and shows you options for fixing them.
The top five common issues cover deprecated constructs; accessor methods and code rationalization of sequence macros. For each issue, we aim to show you the simplest, and most effective workaround.
The UVM-IEEE standard documents the UVM API but does not provide a library. Most companies will use the UVM-IEEE Reference Implementation library provided by Accellera. This TB also discusses the Accellera library and the significance of the @uvm-ieee, @uvm-contrib and @uvm-accellera library content groups.
You can find this TB on support.cadence.com at the following link.
As mentioned, "Top Five Things That Break with UVM-IEEE" is the latest in a series of advanced UVM Training Bytes.
These come from Cadence advanced UVM training classes. As "advanced" means different things to different people, the agenda for each advanced UVM class is customized from a library of modules. We can also create new modules for content not yet covered by the library. Good news is that these classes are still available - contact your local training advisor for more information. Even better news is that Cadence is gradually releasing our advanced UVM modules onto support.cadence.com for free. Over 50 advanced UVM TBs are currently available, ranging from simple short TBs such as "What is UVM Register Modelling?", to multi-part TBs covering complex topics, such as "UVM Report Customization" and "Concurrent Sequences and Interrupt Modelling".
Check out the full range of advanced UVM TBs at the following link:
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The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended Training
System Design and Verification Training Deep Dive: Part 1
System Design and Verification Training Deep Dive: Part 2
System Design and Verification Training Deep Dive: Part 3