System Design and Verification Training Deep Dive: Part 3

As we continue the System Design and Verification Online Training deep dive, we’ll be covering C++ and SystemC languages. These courses should be taken after the recommended courses in Part 1 and Part 2, as the previous parts will provided helpful context for what you’ll learn in these courses.

After completing all the courses in Part 1, 2, and 3, you can expect to have a better understanding of the Cadence system design and verification solutions. With your knowledge, you’ll be able to reduce integration time, accelerate IP development and early software development, integrate system validation, and so much more to improve simulation, acceleration, emulation, and management capabilities!

Let’s look into what the remaining courses will teach.

Summary

	1.	C++ Language Fundamentals for Design Verification
	2.	SystemC Language Fundamentals*
	3.	SystemC Transaction-Level Modeling TLM2.0

*One of the top courses among students and professors

C++ Language Fundamentals for Design and Verification

This course introduces the C++ programming language for those that will use C++ for design or verification. In this course, you write and execute C++ code that includes C++ classes, member variables and functions, constructors, destructors, inheritance, and polymorphism.

After completing this course, you will be able to:

• Write and execute
  • A simple C program
  • A simple C++ program with classes and objects
• Define
  • Class constructors and destructors
  • Aliases for variables by defining reference variables
  • Data common to all objects of a class by defining static members
  • An interface common to multiple classes by defining pure virtual functions
• Achieve the best compromise between program reliability and runtime performance
• Simplify the application interface
• Describe and explain implicit type conversions automatically done by the compiler
• Diagnose incorrect program behavior
• Store and manipulate data by using standard containers and standard algorithms
• And more!

SystemC Language Fundamentals

This course teaches the IEEE Standard 1666-2011 SystemC Language. You perform the lab exercises using the Incisive Enterprise Simulator XL.

After completing this course, you will be able to:

• Identify where SystemC fits in your design flow
• Construct and simulate SystemC modules
•  Model design data using SystemC data types
• Model design behavior using SystemC processes
• Define, implement, and utilize SystemC interfaces
• And more!

SystemC Transaction-Level Modeling (TLM 2.0)

This course teaches the IEEE SystemC TLM 2.0 library. The TLM 2.0 library provides model interoperability for memory-mapped SoC platforms. The library addresses the use cases of software application development and hardware/software integration, software performance analysis, hardware architecture analysis, and hardware functional verification. The library simultaneously meets the corresponding requirements for interoperability, relatively accurate timing, high simulation performance, and controllability and observability for debugging efforts.

After completing this course, you will be able to:

• Briefly describe the general purpose of TLM and the specific features of IEEE SystemC TLM 2.0, and map your objectives to the loosely-timed or approximately-timed modeling style
• Model a simple loosely-timed virtual platform, using the blocking transport interface, generic payload, convenience sockets, and temporally-decoupled processes
• Model a simple approximately-timed virtual platform, using the non-blocking transport interface, generic payload and extensions, base protocol and extensions, and convenience sockets, and adapt between the blocking and non-blocking transport interfaces
• Debug your virtual platform, using the direct memory interface, debug transport interface, and analysis interface, FIFO, and ports
• Learn More!

How to Enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk

Completing the courses from Part 1, 2, and 3, will set you up for success! You can take your knowledge to the next level by earning a digital badge to share with your peers and future employers on your resume, email signature, and even social media profiles, like LinkedIn! Keep following the Cadence Academic Network blog for other exciting topics, updates, and announcements.