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We’re excited to share the last blog for the Digital Design and Signoff Training Deep Dive. We’ve shared the courses you need to take for Synthesis and Test, and Implementation, now we’re going to share the courses for Silicon and Signoff. Just a couple more courses to go until you’re a design pro!
In these courses, you’ll learn about Cadence Tempus Timing Signoff Solution, which is a static timing analysis tool that makes scaling to hundreds of CPUs quick, even for large designs. The Cadence Voltus IC Power Integrity Solution is a power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies on a power delivery network (PDN) or the power grid of a chip. The Voltus tool is of particular value to designers by providing a better understanding of the power grid strength, as well as debugging, verifying, and more!
We’re pulling the recommended training flow from the Learning Maps, which structure the iLS Online Training courses into technical areas and difficulty levels. Some of the below courses offer a Digital Badge. Once earned, you can showcase that you’re Cadence Certified on your resume, email signature, and across social channels like LinkedIn. For best results, it is recommended that you take the courses from Part 1, then Part 2, and then Part 3, but if you would like to start at this point, you should preface these courses with the Basic Static Timing Analysis course.
Tempus Signoff Timing Analysis and Closure*
Voltus Power-Grid Analysis and Signoff
*One of the top courses among students and professors
This course is a detailed exploration of the Tempus Timing Signoff Solution, which supports distributed processing and enables fastest static timing analysis with full signal integrity (SI) and glitch analysis, statistical variation (SOCV), and multi-mode and multi-corner analysis. In this course, you analyze a design for static timing and signal integrity issues, test parallel processing techniques, run Tempus ECO to analyze the timing issues on large designs at the signoff stage, and fix them using the Innovus Implementation System.
After completing this course, you will be able to:
This is an Engineer Explorer course for designers who need a comprehensive and detailed understanding of power-rail analysis for advanced processes.
In this course, you explore the need for power-rail analysis and use the Voltus IC Power Integrity Solution software to run static and dynamic power and rail analyses. On the first day, you identify the features of Voltus, import design data, and run design sanity checks. You also run early rail analysis using the Innovus Implementation System. You create a technology library and power-grid libraries. On the second day, you run static power and rail analyses. You also run dynamic power and rail analyses and explore more advanced power-rail analysis and decap optimization.
We hope that these courses, in addition to the Synthesis and Test and Implementation blogs, will set you up for success in becoming a design pro. You’ll have a deeper understanding of Cadence's digital design and signoff technologies. We will continue to break down the top 15 online training courses among students and professors into their different technical areas and share the supporting courses that go along with them, so stay tuned for the blogs to come that will deep dive into courses related to custom IC, system design, and verification.