Student Story: Min-Chun's Contribution to Cell-Aware Test

4 Oct 2019 • 2 minute read

(from left to right) Erik Jan Marinissen, Min-Chun Hu, and Zhan Gao Let me introduce myself. My name is Min-Chun Hu, a master student majoring in electrical engineering (EE) at the National Tsing-Hua University (NTHU) in Hsinchu, Taiwan. Currently I am doing a nine-month internship at the world-renowned research institute imec in Leuven, Belgium. At imec, I have the opportunity to collaborate on projects with Cadence Design Systems and the Technische Universiteit Eindhoven in the Netherlands.

Traditional fault models in industrial IC testing target interconnects in between the standard cells of a gate-level netlist and focus on stuck-at and transition faults. However, with CMOS technology scaling, more defect locations occur inside the library cells, and as they are not explicitly targeted, they might not be detected by tests based on traditional fault models. A new test-generation approach, named cell-aware test (CAT), explicitly targets intra-cell defects. My project focuses on improving the cell-aware test tool flow from Cadence for the most advanced CMOS technologies; in November the research team I am now part of will publish a conference paper on using Cadence’s cell-aware test generation flow on a 3nm FinFET CMOS library from imec.

There are multiple steps in the Cadence CAT tool flow: first, we generate a transistor-level netlist for all library cells on the basis of their layout. Then, we extract the potential cell-internal open- and short-defect locations from the netlist. After that, we are able to find which cell-level test patterns detect which potential defects. Cadence’s advanced software tools Pegasus, Quantus, Spectre, and Modus play an important role in the CAT flow.

This is the first time I traveled on my own to a country so far away from Taiwan. Despite the uncertainty, I took advantage of this great opportunity to get out my comfort zone and see the world. It was worth the risk! imec provides an environment that allows me to be creative and productive. The cooperation with Cadence is also very exciting because having access to advanced EDA tools is such a great opportunity for an EE student like me.

Thanks to my manager at imec, Erik Jan Marinissen, and my senior, Zhan Gao, with their guidance, I have learned a lot regarding cell-aware research. Thanks to Anton Klotz, University Program Manager at Cadence in Munich, Germany for giving me this chance to share my experience, and to Joe Swenton, Software Architect at Cadence in Endicott, NY, USA, for giving me lots of support. Special thanks to my professor at NTHU, prof. Cheng-Wen Wu; without him, I would not have had this opportunity.

I have learned a lot from my internship at imec, and I look forward to continuing to learn and improve myself in the future.

Learn more about the project

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Story written by Min-Chun Hu and published by Kira Jones.