Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification

Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity.

Bonjour!

In this post, I will explain how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. I will reuse the behavioral models I described in my blogs.

Verilog-AMS Disciplines

Verilog-AMS HDL allows the definition of nets based on disciplines. This is a key concept for mixed-signal simulation.

• Verilog-AMS lets you declare conservative disciplines. The electrical discipline is widely used. Discipline defines the nature of signals in terms of electrical characteristics. This electrical conservative discipline provides access to voltage and current on the ports and is computed inside the analog solver. Electrical disciplines are defined in the file named disciplines.vams.
• Verilog-AMS also provides the concept of discrete disciplines. They are computed inside the logic event simulator.

How can you create a logic1 discipline?

Figure 1: Source code of the logic1 discrete discipline

When two or more ports with different disciplines are connected on the same node, at elaboration, the simulator detects this node. This node becomes a ‘mixed-signal’ node. When the simulator has a user-defined connect rule for such connections that have a discipline mismatch, it inserts the corresponding connect module. If not, an elaboration error is displayed.

What is a connect module?

A connect module is a behavioral model that converts a signal, for example, a logic with 0,1 to the analog or equivalent electrical representation in electrical discipline. This is like a level shifter, but here the conversion is executed between two disciplines. It creates a “bridge” between these two domains.

Connect modules have two functions:

• Translation between the digital (logic) and analog domains
• Using logic and analog information to control the propagation of digital signals and analog signals.

In analog mixed-signal simulation, the designer must connect an instance logic port to an instance electrical port. A simulator based on Verilog-AMS lets you do this with ease. When the AMS simulator reaches the elaboration steps and detects mismatched port types connected on the same node, it automatically inserts a connect module defined by this Verilog-AMS connect rule. This happens only if there is an existing connect rule explaining how to perform such conversions.

How can you create a logic-to-electrical (L2E) connect module?

Read the previous blog to know about the logic-to-electrical conversion behavioral modeling. Copy the L2Econv behavioral code and replace the keyword module by connectmodule. The work is done efficiently. The following figure shows an L2E connect module. The comments explain the behavioral code.

Figure 2: Source code of the L2Econv connect module

How can you create an electrical-to-logic connect module?

Read the previous blog that explains the electrical-to-logic conversion behavioral modeling. Copy the E2Lconv behavioral code and replace the keyword module by connectmodule. The following figure shows an E2L connect module. The comments explain the behavioral code.

Figure 3: Source code of the E2Lconv connect module

How can you specify that the AMS simulator must automatically insert the L2Econv or E2Lconv at elaboration when there is a connection between two ports with a discipline mismatch?

Verilog-AMS standards provide the solution using the connect rule concept. They let you set up a rule to smartly connect a dedicated connect module when an input logic port is connected to an electrical port.

You can also define a rule explaining which connect module to insert when an electrical input port is connected to a logic output port. Here we show how you could define the connect module voltage in the connect rule and propagate it to the L2Econv.

Figure 4: Source code of the connect rule 

In the previous connect rule code, we used three Verilog-AMS keywords, connectrules, connect, and endconnectrules.

Here, the connect rule named amsSignalCR specifies that two modules, L2Econv and E2Lconv are the connect modules to be automatically inserted whenever a signal and a module port of disciplines logic1 and electrical and are connected.

CM Auto-Insertion mode

There are two ways to enable the automatic insertion of connect modules with Spectre AMS Designer simulator.

The first method uses only connect rules and the simulation is launched with this xrun command. Ensure that you specify the -amsconnrule command.

­ ­xrun -64 -clean -ams_edb -gui -debug -input probe.tcl tb.vams inv.v E2Lconv.vams L2Econv.vams amsSignalCR.vams -amsconnrules amsSignalCR -setd "cell-inv- logic1"

With Spectre AMS designer simulator, the Verilog-AMS file containing the behavioral code for user-specified connect modules is passed to the xrun command. The Verilog-AMS compiler processes this file.

The second method uses an AMS Control file. For example, the given figure shows the amscf.scs file that contains an amsd block and IE card.

Figure 5: Source code of the amscf.scs file 

This is a Cadence proprietary method to insert connect modules. The IE card provides support for setting up parameters. This ensures strong flexibility of the seven scope statement features. For example, you can apply this IE card globally or on a net, instance, port, etc.

The AMS simulator automatically inserts the connect modules hierarchically during elaboration. The connect modules are inserted based on the node discipline resolution and port direction at each level of the hierarchy.

Using SimVision MS Debug with the Testbench (TB) as displayed in the figure, we observe that the connect modules are automatically inserted at their associated conversion point. They are visualized with the red colored diamond. The connect module name is also backannotated.

Figure 6: SimVision MS Debug Testbench schematic with the two automatically inserted connect modules. An electrical sine voltage source drives a digital logic inverter. This digital logic inverter drives an electrical resistor.

In the design TB structural netlist, these connect modules are invisible. SimVision MS Debug reveals the automatic insertion of connect modules that is usually invisible. See the red diamond in the previous figure.

The waveforms for the simulation results are as follows:

Figure 7: SimVision MS Debug plots the V(clk) electrical sine signal (red colour) l, the input logic inverter signal (green colour), and the V(clk) electrical signal on the resistor port.

Interactive Debugging Using SimVision MS Debug

You can send an L2Econv instance to the Source Browser, perform a step-by-step operation investigation, or set breakpoint at a specific line as shown in the figure. The breakpoint causes the debugger to pause the simulation when it reaches the line execution. This allows to examine the input and output, the internal register, and variables values. When you launch a batch simulation, you cannot use the interactive debugging feature to understand the model line by line and its step-by-step operation or study the source code operation in detail. The interactive debugging feature provides you the visibility of the code operation. The invisible changes in the internal analog and digital variable values become visible.

Figure 8: SimVision MS Debug on the L2Econv connect module

In the above figure, we observe that the simulation is paused because a breakpoint is set up at line number 21.

Conclusion

• In general, a mixed-signal engineer should be familiar with the concept of disciplines, connect modules, and connect rules.
• I explained the creation of connect modules and connect rules with the Spectre AMS Designer.
• With Spectre AMS Designer, it is very easy to create custom connect modules. Cadence already provides you the very powerful Universal Connect Module (UCM) by default in the installation.
• The most user-friendly method to enable the automatic insertion of connect module is to use the IE card flow.
• SimVision MS Debug is very valuable for interactive debugging of connect modules and connect rules.

In my next blog, I will explain the innovations of the Universal Connect Module (UCM). They incorporate the latest and advanced features you might need.

Hope you are now excited to use SimVision MS Debug to create your own custom connect modules and connect rules and optimize them! If you need more details, contact your Cadence Customer Support team.

~ Andre Baguenier

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Start Your Engines

The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, subscribe and submit your email ID in the Subscriptions box.