Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout

The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creating these IC designs, by maximizing speed and silicon accuracy throughout the design process. The methodology also covers the key design domains of analog, custom digital, and RF, and supports their integration with digital standard cell blocks. 

Design Flow Stages

The following figure illustrates the 5 key design stages in the Custom IC design methodology and the tools used to execute them. This is the third blog in the Custom IC design Flow/Methodology series covering the Circuit Layout design stage. In this blog, we will be highlighting the Rapid Adoption Kit available on the Cadence Learning and Support portal that you can download for free and use as a test set up to try out the various stages of the Custom IC design flow. This blog focusses on design reuse, creating abstract views, and gives an overview of layout generation and floorplanning and an introduction to special power routing sections of the design.

Design Reuse or Engineering Change Order (ECO)

Design reuse or Engineering Change Order (ECO) prevents the need to redesign the entire layout if a schematic specification changes. The mismatches between the updated schematic and existing layout are identified. The parameters are updated, Virtuoso Layout Suite XL can be used to fix any shorts or opens. Then physical verification is performed to confirm there are no violations.

Abstract View Creation

The Abstract Generator is used to create a ‘lighter’ version of blocks, containing only the boundary, pin, and blockage information, which improves the performance of top-level placement and routing. After the place-and-route is complete, the abstracts are replaced back with the layouts.

Layout Generation from Scratch 

You can use the automatic placement and routing features from Virtuoso Layout Suite XL to create a fresh layout from a schematic. You can also use the available routing and placement features to control the I/O pins, boundary size, and device generation. It helps to first do a rough placement, followed by automatic routing using the Virtuoso Space-based Router.

                                 

Floorplanning  

Typically, lower-level blocks are not ready during top-level floorplanning. So, you can use soft blocks to represent the final blocks instead of frozen layouts, which are also referred to as hard blocks. Working with soft blocks brings the flexibility of having pins that are not yet frozen and the PR boundary too can be defined based on area estimation and the aspect ratio of the layout can be altered. At this point, you could also leverage the pin optimization feature and use the soft block editing commands to get a better floorplan.

        

                                                                                     

Routing Critical Nets and Power Planning

After the floorplanning is complete, you can use the Virtuoso Space-based Router to route the top-level critical nets. You can use the power routing feature to complete the power planning.

  

To try out the Custom IC Design flow, you can download a series of RAKs from the Cadence Learning and Support website. In this RAK series, each stage in the Custom IC Design Flow and Methodology is explained in detail, supported by a downloadable test database to help you try out the steps. The RAK series begins at the introduction of the design flow, followed by the schematic and layout design of the Sample and Hold ADC block, which is then followed by a pre-layout simulation setup and run. Then the RAK covers extraction of the individual blocks inside the top-level Flash ADC design, followed by a final post-layout simulation analysis to ensure the pre- and post-layout results are consistent and the specifications are met. The GDSII (Graphic Database System II) file is created as a final step, which can then be sent to the foundry for fabrication. You can run each stage in the RAK independently, or work your way through the entire flow.

To read more about the next design stage - Circuit Physical Verification and Parasitic Extraction - in the Custom IC Design flow, stay tuned for our next blog in the series.

For more information on Cadence Custom IC circuit design products and services, visit www.cadence.com.

Related Resources

Rapid Adoption Kits	Custom IC Design Flow/Methodology  Custom IC Design Flow/Methodology: Schematic Capture & Circuit Simulation Custom IC Design Flow/Methodology: Circuit Layout
User Guides​	Virtuoso Schematic Editor User Guide Virtuoso Layout Suite XL User Guide Virtuoso Module Generator User Guide Virtuoso Abstract Generator User Guide Virtuoso Floorplanner User Guide Virtuoso Space-based Router User Guide Virtuoso Glossary
Blogs	Virtuosity: Custom IC Design Flow/Methodology – Introduction Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Simulation

Contact Us

For any questions or general feedback, please write to custom_ic_blogs@cadence.com.

Happy reading, and stay safe!

Kanwal Bassamboo, Sandeep Kumar Singh, Ashish Patni

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more.