Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 2 (LVS)

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso Multi-Technology Solution, Virtuoso Electromagnetic Simulations, and Virtuoso RF Solution. So, how does Virtuoso meet Maxwell? Now, Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world, along with the nuances of RF, microwave, and high-frequency designs. Watch out for our posts on Mondays.

Welcome to the second blog on custom passive device authoring (CPDA). RF designers know that passive metal devices, such as inductors or transformers, represent a special challenge in RFIC designs. In some parts of the overall design flow, passive metal devices must be treated as any other device. For example, if you need a device model for circuit simulation, EMX Designer can be used to extract it. However, for many physical effects, a metal inductor on Metal10 behaves like any other metal routing on Metal10. Physical laws do not depend on whether you define metal shapes as devices or as interconnects. For example, a metal device experiences electromagnetic coupling to adjacent nets, and it might be exposed to electromigration. One of the Virtuoso Meets Maxwell blogs already emphasizes that a metal inductor cannot always be characterized as an isolated device. 

Indeed, there is yet another facet to this topic. On the photomask for Metal10, there is no difference whether a metal shape is part of a device or an interconnect—the gds format used to fabricate the photomask just specifies that there is Metal10. However, many state-of-the-art electronics design automation (EDA) flows are based on the distinction of devices and interconnects. EDA tools running on an IC layout must identify which shape is part of a metal device and which one is part of the interconnect. For PDK devices, marker shapes are used for this purpose.

The whole topic of a metal inductor not being characterized as an isolated device becomes important with the use of custom metal devices that are user-defined and not part of the foundry-provided PDK.

One of the flows that is strongly based on the distinction between devices and interconnects is the LVS is the Parasitic Extraction (PEX) flow. LVS extracts layout devices and how they are connected. From that, it generates a corresponding layout netlist without interconnect parasitics. For final signoff, it is strongly recommended to use the manufacturing database as input, which is gds. To extract the parasitics of interconnects, a PEX tool like Quantus is used. To correctly handle custom passive devices in the LVS-PEX flow, marker shapes must be added. Based on these marker shapes, CPDA unambiguously identifies a device and creates a device signature.

The first blog on CPDA illustrates automatic marker shape generation. In this second part, let us see how to automate the LVS-PEX flow when custom passive devices are used in the design. Fig. 1 recaps the overall CPDA flow.

Fig. 1: Custom Passive Device Authoring Flow

After marker shape generation, Generate Device Signature creates all additional data that is needed to include in the custom device for a top-level LVS. Besides auCdl view and CDF settings for CDL, netlisting includes the generation of a PVS or Pegasus devices signature mainly. Fig. 2 shows how to launch signature generation from the Virtuoso Electromagnetic Solver Assistant.

Fig. 2: Device Signature generation with CPDA

This CPDA flow step starts the PVS or Pegasus Device Signature Generator in batch mode. The technology-specific information is taken from devicesMap.txt, a user-defined ASCII file. A device signature is an LVS representation of a device. It stores the pattern of all device shapes in a signature string. During top-level LVS, Pegasus compares the shapes that are present in the layout with the shapes that are stored in the device-specific signature. It is a kind of pattern-matching approach. If the shapes in the layout match the shapes stored in the device signature, LVS identifies a match. In case the shapes differ, Pegasus LVS reports a malformed device. Fig. 3 shows an example of such a signature file.

Fig. 3: Exemplary device signature file

You find more information about device signature generation in the Device Signature Generator chapter of the Cadence Pegasus User Guide. To support an unlimited number of custom passive devices in a design, a unique label and a small add-on rule file for Pegasus is needed and therefore, is auto-generated.

The device signature (dev_signature) and add-on rule file (ext_rule) are stored in the 5x-data structure of the custom device, as shown in Fig. 4.

Fig. 4: Device signature (dev_signature) and Pegasus add-on rule file (ext_rule) stored in the 5x-data structure.

After this step, the new custom device is fully characterized and ready to be used in the design.

For top-level LVS, a Pegasus pre-trigger function scans the design for custom devices and adds the device signature and the add-on rule file to the list of rule files for Pegasus LVS (see fig. 5).

Fig. 5: Top-level Pegasus LVS using device signatures for custom passive devices.

Now, the top-level LVS and Quantus parasitic extraction can be run as usual.

To conclude, after running CPDA to create a device signature, custom passive devices can be used like any standard PDK device. Pegasus LVS and, subsequently, Quantus parasitic extraction manage these devices appropriately.

In these two CPDA blogs, we focused on the automation of the LVS flow in order to remove the need for tedious manual tasks and increase design efficiency. An additional advantage of CPDA is the closure of verification gaps that still exist in today’s physical signoff flows. More details on this topic will be the subject of another blog.

Therefore, stay tuned and look out for upcoming Virtuoso Meets Maxwell blogs to learn more about custom passive devices or other RF design challenges, and how advanced flows in Virtuoso RF Solution help designers address and resolve these challenges.

Claudia Roesch

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

Contact Us

For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com.

About Virtuoso Meets Maxwell

The Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching! Subscribe to receive email notifications about our latest Custom IC Design blog posts.