Virtuoso Meets Maxwell: Quick Start for Virtuoso RF Solution

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

The shift to heterogeneous integration of module designs implies a transition from PCB-styled flows and methodologies towards IC-styled flows. Cross-fabric design and verification methodologies for multi-die packages have become indispensable parts of any advanced module design flow. Cadence is uniquely positioned to lead and spearhead this transition. To address the challenges of a rapidly increasing market driven by 5G, Automotive, and IoT applications, Cadence has augmented the widely used Virtuoso Design Environment with a MultiTech Framework.

The Virtuoso MultiTech Framework extends tools and methodologies already familiar to IC designers into the module space. It enables various Virtuoso schematic-driven IC-package, co-design, and co-verification flows. The seamless integration of multiple Electromagnetic Solvers allows you to pick the most suitable engine for the application, run cross-fabric EM extraction, and automatically stitch the results from different solvers back to the golden schematic.

Further, Virtuoso MultiTech Framework allows a choice between Virtuoso Layout Suite or SiP Layout Option for package layout authoring. The new Virtuoso Allegro SiP Layout implementation flow–and other related topics–is covered in previous blog of this series.

Given the broad technical range of this topic, and the many different tools and flows that are involved, Cadence started an initiative to showcase these new methodologies and enhanced functionalities in a comprehensive Rapid Adoption Kit (RAK). The RAK will evolve with the increasing functionalities available in the Virtuoso System Design Platform. Continuous updates of the RAK will be made available on Cadence Online Support (COS) to guide you on your search for a more efficient methodology for module design.

The RAK–its first version got published with ICADVM18.1 ISR13–includes multiple self-contained chapters addressing different sub-flows and sub-solutions all combined in solutions based on the Virtuoso MultiTech Framework.

All chapters of the RAK are based on a design database of an RF-Front-End-Module assembled on an 8-layer laminate package. The database consists of an LNA, a PMIC, and a PA module designed in different generic Cadence technologies (g-PDKs). The PA modules includes a flip-chip MMIC IC. LNA and PMIC are wirebonded ICs. The implementation of the Package-on-Package design is fully supported in the Virtuoso RF Solution. Based on this system design, the RAK explores challenges and reconciliations of a typical system design flow and showcases various solutions how to best address these challenges.

The center piece for design implementation and analysis flows is a golden system-level schematic that drives physical layout implementation and verification, cross-fabric parasitic and electromagnetic extraction, and post-layout system simulation and optimization.

The first version of the RAK focuses on the Virtuoso RF Module Implementation and the Virtuoso SiP Implementation flows.

Module 1: Create Package Schematic and Run Pre-Layout Simulation covers:

Generation of package schematic with multiple dies, Surface-Mounted-Devices (SMDs), and embedded package components.
System-level pre-layout simulation using the Virtuoso ADE Product Suite and Spectre Simulation Platform/Spectre RF Option.

Module 2: Virtuoso RF Module Implementation Flow covers:

Package layout authoring in Virtuoso layout using Generate From Source and component placement.
Wire-bonding of an IC footprint by generating bond guides, bond fingers, and bond wires.
The bond wire profile is stored in the Virtuoso technology file.
Interactive package-level routing with push and shove and dynamic voiding.
Edit-in-Concert, Layout-vs-Abstract verification, and correction of IO pad locations.

Module 3: Virtuoso Allegro SiP Implementation Flow covers:

Tight integration between Virtuoso schematic and SiP Layout Option. It enables you to drive package layout authoring in SiP Layout Option from a Virtuoso schematic.
Launch of SiP Layout Option directly from a Virtuoso schematic.
Generation From Source from SiP Layout Option to create an initial layout based on the Virtuoso schematic.
Use of Check Against Source in SiP Layout Option to compare against the Virtuoso schematic.
Use of Update Component and Nets in SiP Layout Option to propagate changes from the Virtuoso schematic to the SiP Layout.

Stay tuned for the upcoming blogs of the Virtuoso Meets Maxwell series as they will continue to tell the exciting journey of the Virtuoso RF Solution.

Claudia Roesch

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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