Virtuosity: Conserve Power—Importing and Exporting Power Intent

20 Nov 2020 • 6 minute read

‘Conserve Power' is a series of blogs that gives a sneak peek into the world of low power verification. It uncovers the functionality and potential of Virtuoso Power Manager, which lets you specify and manage the power intent for your designs. Watch out for our posts in this miniseries every Thursday between now and end of December.

I believe till this point in the Conserve Power blog series, you are aware and appreciate the importance of Virtuoso Power Manager to uncover the power-related issues in your designs, but this doesn’t end here. In the Running In-Design Checks blog, Manish discussed the In-Design checks and how they make the life of a designer easy by providing a mechanism to catch the architectural issues related to low power design elements, early in the design cycle. In this blog, I will focus on the key enablers, which are required before the power-aware designs undergo the verification cycle. This is the ultimate test that confirms the robustness and efficiency of a design.

The Verification Challenge

The increasing complexity in terms of design’s power architecture and its power management has an associated room for something going wrong during implementation. The end objective of every designer is to mitigate the cost to implement and verify power-aware designs by ensuring completeness and correctness of the power intent of the design. It’s now a proven fact that the power intent-based approach has many advantages considering the power-aware verification. The verification can be done early in the design cycle. Not only does this help catch the power-related bugs sooner but more importantly it helps with defect rectification on the actual design rather than on the netlist alone. A comprehensive approach for low power designers can be to augment the simulation-based (dynamic) power verification with formal (static) power verification to have an exhaustive mechanism for catching power-related issues.

Keeping the context limited to static power-aware verification, what are the requirements that a good solution must address? Let us look at what Virtuoso Power Manager has to offer.

How Does Virtuoso Power Manager Help?

The mixed-signal designs are bound to have many flavors, such as analog-centric designs with relatively less digital logic, a schematic-driven flow with analog-on-top (AoT) methodology, and a digital-centric design where analog and mixed-signal logic is imported using a netlist-driven flow. Virtuoso Power Manager has significant offerings for these flows.

In a conventional mixed-signal IC design flow for digital logic implementation, the power intent (IEEE 1801—traditionally termed as Unified Power Format, UPF) remains an important input along with the design intent (the netlist—RTL/Verilog). The digital content, however, must be brought inside the Virtuoso platform for chips integrated using the AoT flow. This requires importing a schematic from a synthesized Verilog netlist. The schematic created using a synthesized Verilog netlist would not have the power and ground connectivity information, which is a prime requirement if you want to run static power verification on the design. This would also be a requirement for physical verification of the design. So, how do we bring in the power connectivity information in the design schematic?

This is where the Import flow of Virtuoso Power Manager comes to the rescue. The import flow is a top-down flow that helps to build the power connectivity into the functional schematic of a complex hierarchical digital block if its power intent (IEEE 1801) is already available. For running the import flow, you need to first set up the design by providing the power-specific information in the Virtuoso Power Manager setup and then use the Import 1801 Power Intent option. To remove the power connectivity generated by Import 1801 Power Intent, use the Remove Imported 1801 Power Intent option.

Power Manager Import Flow

Now that you have a physical design schematic with complete power connectivity, the digital content is completed in a separate, well-defined hierarchy. The analog content is schematic-driven and crafted inside the Virtuoso platform itself. With an IP integrated and completed in terms of its signal and power connectivity, what are the requirements for it to undergo static power verification? It’s the power intent and design intent specifications of the schematic in a format understood by a formal verification tool. For now, let’s focus only on the power intent. It’s a mammoth task if one thinks of manually writing the power intent in a standard IEEE 1801 format for a large hierarchical design. Virtuoso Power Manager using its extraction engine can automatically extract the connectivity-related information of the complete design hierarchy from the design schematic. This data becomes the source of building the power intent for the design. You can set up the design by providing the power-specific information in the Virtuoso Power Manager setup and use the Extract 1801 Power Intent option in the Power Manager Setup form to perform design extraction.

The extracted power intent of the design subsequently needs to be exported in a standard format to be consumed by the formal verification tools for static power-aware verification. You can use the Export 1801 Power Intent option to write the extracted power intent to a file, that is, a design model in IEEE 1801-2009 format. You can also write a basic power model in IEEE 1801-2013 format.

Power Manager Export Flow

Before I conclude it's important to talk about another important aspect, the power intent specification for analog blocks. As the analog logic is built in a bottom-up fashion, there is no well-defined notion of a power intent there. Virtuoso Power Manager helps the analog designers to check the power intent of the analog macros using in-design checks and subsequently generate a Liberty Power model for the analog macros. This Liberty model is further used in static verification at the upper hierarchy level. You can use the Export Macro Liberty Power Model option to export the Liberty power model to a file.

To Conclude

As designs get complex and low power requirements get stringent, time to market is the key. IEEE 1801-based static power-aware verification is the need of the hour and getting designs ready for it is the key requirement. Virtuoso Power Manager automates the task of writing a standardized power intent specification from the design schematic, therefore, making it ready for the power verification step and enabling its integration in the top-level SoC.

What's Next?

Stay tuned to find out about the following topic in the upcoming blog!

Verifying a Design using Conformal Low Power

Happy reading, and stay safe!

Sachin Bhasin

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