Virtuosity: Conserve Power— Running In-Design Checks

‘Conserve Power' is a series of blogs that gives a sneak peek into the world of low power verification. It uncovers the functionality and potential of Virtuoso Power Manager, which lets you specify and manage the power intent for your designs. Watch out for our posts in this miniseries every Thursday between now and end of December.

In the A Preamble to Virtuoso Power Manager and Setting up Virtuoso Power Manager blogs, we focused on the introduction and correct setup for running Virtuoso Power Manager. After we have all the design inputs captured correctly in the setup, we are ready for our next challenging task of checking the design for correctness. 

Today’s blog focuses on in-design checks that offer an easy and convenient way to identify common design issues encountered by the design community while implementing low power schemes. It also helps designers to uncover issues early in the design cycle, avoiding an ECO. 

In-design checks offer designers a platform where they can run a set of pre-configured checks on analog mixed signal designs to catch violations while they are creating the designs. Virtuoso Power Manager works at the transistor level and offers flexibility to validate and further integrate blocks or IPs with an existing power intent using a library or a UPF file format. Virtuoso Power Manager specifically caters to the need of the mixed design community with support for almost all the design scenarios prevalent for low power designs. 

In-design checks offer a wide variety of checks around the low power design arena. A few of the important checks are discussed below with a brief introduction on the working.

Identifying Missing Level Shifters

With the use of multiple voltage islands and variable voltage values, missing level shifters is a very common issue that designers face in analog designs and find it very difficult to catch with either a visual inspection or without running an exhaustive set of simulations. In this check category, Virtuoso Power Manager finds violations in design where a low-voltage signal is driving a high-voltage receiver or conversely. The check also provides designers with the flexibility of defining the correct parameters for custom-level shifters, such as a valid range and compatible voltage values. If it is found that the same is not adhered to at a particular location, a compatibility check violation is flagged. The violation is reported with a detailed message indicating the involved driver and receiver devices and specifying their connected voltage values.

Identifying Missing Isolations

To save power, designers partition their designs in power zones and shut them off when not needed in an active cycle. For a correct implementation of a power shut off scheme, it is required to use an isolation cell at such crossings to avoid any leakage issues in designs.

In this category of check, Virtuoso Power Manager reports violations in design where driver signal can go in shut off mode without an isolation cell present and leave the input hanging. All such violations are flagged during the check and reported as missing isolations in the design. Not only are the missing violations highlighted, but also the correct isolation supplies need to be present for the effective data and clamped feature functionality with use of power states are also checked.

What About Redundant Elements?

Another important task for achieving the most optimum power scheme is to highlight the elements that are not required in designs. These can be remnants of a design porting or a change in power scheme that no longer demands the functionality of either level shifting or isolation. Presence of such cells can lead to an extra power consumption and underutilization of the valuable silicon area. Virtuoso Power Manager, by virtue of its redundancy checks, also helps in catching such violations by highlighting the redundant elements in design.

Advanced Setup Options

The tool offers advanced setup options that can be used to catch violations in most complex design scenarios

• Support for supply rail voltage tolerance: Designers can fine tune the tolerance value based on the margin available so that Virtuoso Power Manager doesn’t flag a violation if the driver-receiver supply difference is within the supplied tolerance voltage value.
• Multiple device thresholds: Designers can define threshold values based on a device model type, and this can help in avoiding false positive violations for intentionally over-driven devices.
• User-defined power states: Designers can define different supply net voltage values, emulating a low power mode scenario or they can toggle the supplies as ON or OFF for a multiple supply design, emulating various low power modes. The tool uses these inputs to catch violations for missing isolation or leakage path issues in the specified power states.
• Support for filtering out the violations: If designers want to ignore a violation, they can use the option of filtering violations based on an easy to set up filter pattern. All such filtered violations are still reported in a separate section in the generated summary file.

Error Browsing

Along with the summary file, a violation database is also generated that can be used to easily browse to the device causing the violation. Easy in-context navigation is provided for each violation using the context menu from the Annotation Browser to choose the desired violation object.

Advanced Checks

There are advanced-level checks that can help designers identify potential leakage paths in designs due to incorrect bulk or floating nets in the design. A few of the advanced checks are as below:

• Unprotected Level Shifter check
• Floating Level Shifter check
• Always enabled Level Shifter
• Unused enable Level Shifter
• Bulk checks

With all the simple and advanced checks in place, the in-design checks feature offers a unique way to ensure quality and correctness of analog mixed signal designs even at the IP authoring stage. The feature helps designers to ensure required design checks are in place and the design is meeting the success criteria as defined.

What's Next?

Stay tuned to find out about the following topics in the upcoming blogs!

1. Importing and Exporting Power Intent
2. Verifying a Design using Conformal Low Power
   
   

Happy reading, and stay safe!

Manish Jain

Related Resources

Virtuoso Power Manager User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

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About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.