Virtuosity: Conserve Power—Verifying a Design Using Conformal Low Power

‘Conserve Power' is a series of blogs that gives a sneak peek into the world of low power verification. It uncovers the functionality and potential of Virtuoso Power Manager, which lets you specify and manage the power intent for your designs. This is the final blog of this miniseries. We will be back with a new miniseries in some time.

If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.

In my previous blog Importing and Exporting Power Intent, I explained how Virtuoso Power Manager helps in generating the IEEE 1801 file, which is a standard format that captures the power intent of the design. Let's look at what happens later. As soon as the IEEE 1801 file is introduced in the design flow, power connectivity of the design also comes into the picture along with the logical connectivity. All low power designs must adhere to the low power specifications mentioned in a power intent specification. To ensure that a design complies with the low power specifications, both static and dynamic checks need to be performed using the IEEE 1801 file. As designs get more complex and the number of test vectors increase, the goal of 100% functional coverage using the traditional simulation-based (dynamic) techniques becomes increasingly difficult to achieve. The long simulation times add to the problem of exhaustive testing of the design and pose a question on the cost-effectiveness of the check. The need of the hour is to introduce formal verification strategies, based on static analysis algorithms, to complement the simulation-based verification. The main requirements that a sign-off formal verification tool should address are:

The tool should be power intent driven.
The tool should have a comprehensive set of structural and functional checks to verify the low power design techniques in your design.

Cadence® Conformal® Low Power does a great job in meeting these requirements.

Preparing For Verification

The IEEE 1801 file is generated by Virtuoso Power Manager from a fully connected design schematic that has both signal and power information. The static verification flow using Conformal Low Power works on a netlist with power and ground nets.

Conformal Low Power Verification Flow

We have three main requirements for the verification flow to work, the IEEE 1801 file (power intent), a physical Verilog netlist with power and ground information, and the verification tool (Conformal Low Power). Does that mean you need to juggle between different interfaces to make this thing work? The answer to that is “NO”. Virtuoso Power Manager provides an integrated interface that enables generating the required inputs for verification as well as performing the verification.

Virtuoso Power Manager Integrated Verification Flow

The Prepare CLP option in Virtuoso Power Manager generates the desired inputs required for Conformal Low Power verification run in the following sequence.

The Prepare CLP form provides an option to specify an existing power intent (IEEE 1801 file). If the power intent is not available, the power intent is exported from the design post extraction.
The switch view list specifies the views that the tool traverses to find the power and ground connectivity information.
The Prepare CLP form provides an option to specify a netlist customization file (.simrc), which enables the generation of a physical Verilog netlist in the desired format. The physical Verilog netlist is generated in the background when preparing Conformal Low Power for verification.
A source file (dofile) is generated with the customization options required by Conformal Low Power to run the static verification.
A detailed log file is created to help debug any issues encountered while preparing for Conformal Low Power verification.

After the Prepare CLP command is run successfully, the Run CLP option triggers the actual verification engine to perform static analysis based on the inputs. After the verification run is completed, a detailed report shows a log of all the steps performed during the verification flow and highlights the run violations along with the associated severity, such as Error, Warning, or a Note. After the causes for the violations are debugged, the design is fixed for the reported violations or the violations are waived off, as appropriate.

We'll be back !

As quoted by Kate Lord Brown – The end is never the end. It’s always the beginning of something. I strongly believe that we have a technology that can help low power designers in their design cycle timely by avoiding any last-minute surprises. We will continue to develop, improve, and share more offerings in the low power space.

Happy reading, and stay safe!

Sachin Bhasin

Related Resources

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Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.

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