'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection between stacked ICs, interposers, packages, and boards. Bump locations, connectivity, and other attributes are the basis for creating TILPs, which we combine to create system-level layouts.

If the term TILP is new to you, Kerry Judd’s primer might be a good read:

TILP! What’s a TILP?

How do we tell the Virtuoso platform about our bumps? 

The best way to identify your bumps is to set the bump layout’s CellType to coverBump.  Die Export will treat instances of this cellview as bumps.  The connectivity on the terminal of these instances will transfer to the die footprints TILP.

Make sure your bump cellview has a physical pin, and note the layer of your pin. You’ll provide this information to Die Export. This layer’s shape will represent the bump in the resulting TILP.

When your bump instance is placed in your die layout, you’ll need to make sure you have connectivity on the bump terminal. If you have bump instances with no connectivity, but you’d like to export them anyway, just check the Include unconnected IO Pad cells as shown above.  These bumps may be uncommitted or their connectivity is TBD, but their presence must be accounted for in the adjacent fabric.

Wait, I can’t edit my die layout! Isn’t there another way?

Yes, there is. We realize there will be times that you simply cannot edit the layout of one or more components. Maybe it isn’t your IP. Maybe the data is version controlled, and any edit will trigger a need to re-validate. Whatever the reason, we’ve got your back.

We now support a text-based flow. You can simply tell us what label layer(s) were used for your bumps.* 

And there you have it. You’re ready to build your system-level schematic and layout!

*Be aware that the text-based flow is somewhat less robust, and Edit-In-Concert functionality may be limited by exporting die in this manner.

Related Resources

• Virtuoso RF Solution
• What’s New in Virtuoso (ICADVM18.1 Only)

For more information on Cadence circuit design products and services, visit www.cadence.com.

Contact Us

For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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Brian LaBorde