Virtuoso Meets Maxwell: Enabling System Analysis And Implementation Through Libraries

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Welcome to a post on how to create component and padstack libraries for use in the Virtuoso platform-driven multiple technology flows. This post describes the tasks of a librarian, who must assemble component IP from various sources and create the views and documentation that can be used by designers.

Previous post talked about Unified Libraries as a crucial enabling step for interoperability between flows and tools. In a multi-technology flow, TILP (Technology Independent Layout Pcells) is used to interface from one technology to the other. For example, the bumps used to connect a die to a package can be placed in a technology-independent library (not the die or package library). The instantiation of the padstack in a design that is placed in a package library evaluates the Pcells and re-layers appropriate shapes to the correct cross-section layers for creating the desired electrical connections. In this post, we will focus on which tool can be used to create TILP views, footprint views, and schematic symbols for different type of components.

Consider this system assembly where a module is designed separately and placed on a package. The module is a Power Amplifier (PA) with a MMIC designed in SiGe50 that is placed on an 8-layer laminate package containing a 45nm CMOS Low Noise Amplifier (LNA) and a 90 nm CMOS Power Management IC (PMIC).

Library elements must be created for each of these components. Let us look at the series of tasks that the librarian must complete to enable the design of this entire system. We will not describe the arguments of each command invocation – that will be covered in future blogs.

1	Create the technology information for the cross-section used in a PA module. If the technology is already available in an existing SiP design, a new library can be created that will hold the cross-section, constraints, and via definitions required for PA Module components.
2	Create discrete part libraries for PA modules (SMD_CAP, SMD_IND, SMD_RES). The SMD instances in a PA module come from a different vendor than the SMD instances in the laminate package.
3	Create the views for the embedded inductor, the COUPLER, and MultiLayer CAP used in a PA module. This may be a design created on the Virtuoso platform and is typically technology-dependent because it contains shapes on layers in a cross-section.
4	Create the views for the MMIC used in a PA module. Note that this IC can be co-designed(the bumps can be adjusted to suit the package). Die export generates an abstract, which can be co-designed. If the MMIC layout is not available, a die text file can be specified that describes the interface. This is a fixed IC and cannot be co-designed.
5	Create the views for the package bump padstacks and store the bump parameters.
6	Create the interface views for the PA module to be used in a package.
7	Create the technology information for the cross-section used in a package. If the technology is already available in an existing SiP design, a new library can be created that will hold the cross-section, constraints, via definitions, and bond wire profiles required for the package components.
8	Create discrete part libraries for the package (CAP, IND, RES). The SMD instances in a package come from a different vendor than the SMD instances in a PA Module.
9	Import the BGA and BGA padstacks used in the package from the SiP Layout Option. IO components can be easily generated in Allegro using convenient wizards.
10	Create the views for the LNA and PMIC used in the package. Note that both these ICs can be co-designed (the bumps can be adjusted to suit the package). Die export generates an abstract, which can be co-designed.
11	Import the Balun and Switch from SiP.

As you can see, the librarian’s job is not easy. And, components change all the time. IC layouts evolve, vendor libraries expand and contract, and embedded components are tuned. Every time something changes, the librarian must update the views. They enable designers to do the fun stuff—while they keep views up-to-date and consistent with each other. Cross-view consistency and validation is a different topic and deserves its own blog.

Stay tuned for more details on each step in future blogs.

Guru Rao

Related Resources

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About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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