'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Hello everyone, after a brief hiatus of a couple of months, I am back again to my miniseries about our Virtuoso RF Solution and Electromagnetic (EM) analysis within that solution. Before we dive into technical details, I want to wish all our readers a safe and healthy time. Hopefully, you can stay safe and healthy with your family and friends, wherever you are.

In the last couple of months, a few exciting things have happened with Cadence’s acquisition of both the AWR and Integrand Technologies, which makes our product portfolio very strong. You can read about that in this blog from Michael Thompson, our Sr Solution Architect.

Picking up from where I left off in Part IV, I want to discuss port setup today. BTW, please feel free to read Part I, Part II, and Part III of this miniseries.

First of all, what are ports? What do these ports resemble? I think it’s important to understand what we are trying to emulate with an EM solver. An EM solver is emulating a measurement setup in the lab using (for example) a Vector Network Analyzer or VNA. Have you ever seen a VNA? The VNA typically has two probes (since many measurements are two port setups). Through these probes, energy is sent into the Device Under Test (DUT) and the resulting two-port s-parameters are measured. It is important to note that each probe consists of at a minimum, two terminals, typically a signal and ground conductor.

The EM simulator emulates a VNA measurement. Instead of probes, EM solvers use ports. Just like the VNA probes, the ports are used to inject EM energy into the DUT and measure the s-parameters during an EM analysis.

Big ports, little ports? How does a port look physically? EM ports should never be too large or too tall, with respect to electrical wavelength. Why? Because as the dimension of the port (distance between the terminals included) increases, it can excite many modes of energy transfer beyond the desired Quasi TEM mode which exists at DC. These modes include higher order transmission line modes, radiation and surface waves.  

A port terminal for an EM simulator using Method of Moments (MOM) formulation is usually a short edge or a point. The ground terminal can be represented by a nearby short edge or port or it could be defined as a conductive plane within the stackup.

What are the typical port types? AXIEM EM solver supports multiple types of ports, for example, single ended, differential, and ports with respect to lower metal or upper metal. All these different port types are exposed to users in the EM Assistant in the Virtuoso RF solution. Both edge and point ports are supported.

Which port should I use and why? My first golden rule is, am I going to compare the resultant s-parameter with a reference and, if yes, what is that reference? Is it s-parameter coming from another EM solver or is it s-parameter coming from a lab measurement?

If you’re comparing measurement data, then the port setup should match the VNA probe tip locations. For example, if the DUT has Ground-Signal-Ground (GSG) pads for measurements, then typically the GSG probes from the VNA will touch the center point of these pads. Hence, the EM ports should also be setup as multi-edged differential ports with a positive edge at the center of the Signal pad, and then two negative edges at the center of the Ground pads. Remember that measurement probes will always have a reference (often mentioned as ground) for each probe and hence, each EM port also needs to be defined as a referenced port (more on unreferenced ports shortly).

On the other hand, if you are comparing with s-parameter coming from another EM solver, then to get an apple-to-apple comparison, you should use the exact same port definitions. At that point, the question is moot whether those are the most appropriate port locations or not; what is rather important is to excite the DUT in the same way as the other EM solver did. Now, one caution about such comparisons. If the reference EM solver is using Finite Element Method (FEM) formulation and you are using AXIEM, which uses MOM formulation, then an exact replication of the ports and boundary conditions will not be possible in most of the cases. This is an inherent issue (does not matter which EM solvers are involved) and expert users will often have to be involved to reduce the discrepancy between the two EM solvers.

How are the unreferenced ports used? It is quite straight forward to understand the concept of a port with a reference or return path, because every signal needs to have a positive and a negative terminal. Reference is important for s-parameter definition. It defines the reference for the port voltage, i.e., defines the return path for the current for a port.

However, what is an unreferenced port? How can a port have no reference? The term unreferenced port is a bit confusing. Indeed, this is a single-edged port, but that does not mean it does not have a reference. In this case the reference is at infinity, which sounds a bit corky, but the math does work out. The reference can also in this case be a ground plane at the top/bottom of the enclosure if it exists. The distance between this ground and the signal terminal of the port should be small as compared to wavelength. 

These unreferenced ports are a big advantage for MOM solvers, when used judiciously. Many times, in IC (or, on-chip) layouts, it is very difficult to find a reference for the port because the return path may not be nearby or may not even exist on the chip (may be on the package or PCB). In this situation, the unreferenced ports can be used. However, be advised that at high frequencies the single-ended port can have non-passivity issue – this is nothing unique to AXIEM, all MOM solvers using single ended ports are subject to this limitation.

Ports with reference to lower or upper metal:

AXIEM supports ports with reference to lower or upper (or both) metal. This can be very convenient in certain situations. For example, in the left-hand side figure below, a simple transmission line structure is shown where the upper signal line is on metal3 and the lower ground is on metal1. If I select the right-hand side edge of the transmission line as a port with reference to lower, then AXIEM will automatically create a reference edge for me directly below the port edge. This port is shown in the mesh in the lower right-hand side figure. Think about the use model here for a second. If I had to accomplish the same manually, then I’d have to create an edge on metal1 directly below the port edge and then create a differential port where the metal3 edge is positive and the metal1 edge is negative. That will involve LOTs of mouse clicks and an unnecessary modification of the layout.

However, caution needs to be used when using the ports with reference to lower/upper metal. If there is no metal below then the port with reference to lower will become very tall as shown in the figure below because the port will extend all the way to the back plane of the IC.

What is port de-embedding? 

De-embedding of an EM port simply means removing the discontinuity associated with a port from the s-parameter. There are well established de-embedding techniques. AXIEM also offers de-embedding for ports. However, do the ports actually need to be de-embedded?

Remember that for on-chip structures the effect of port discontinuity will be small, maybe even negligible, depending on the electrical wavelength, i.e., simulation frequency. In such cases de-embedding will add little to no value.

Also remember that if ports are too close to each other, i.e., they are coupled with one another electromagnetically, then it is not possible to de-embed them.

Finally, de-embedding often requires automatically extending the ports and applying open/short calibrations. For on-chip structures (think of ports on a multi-fingered gate terminals of a transistor) it might not even be possible to do a clean de-embedding.

Because of all of these reasons, it is generally advised to not use de-embedding for AXIEM ports for on-chip structures.

Can ports be automatically defined?

In the Virtuoso RF Solution, user can opt to setup ports automatically. If instances have pins then those can be detected for auto port definition. Also, if the nets have top-level pins then those can also be used to detect ports automatically. However, auto port detection may not always work to the user’s satisfaction. It is always advised to inspect the ports and/or adjust/add manually as needed.

For example, in the case of the inductor shown below, because the pin has been setup with the correct access direction, the correct outside edge is picked automatically. Note that even though the pin is smaller than the width/length of the path of the inductor, still the actual edge of the path is picked as the port.

That’s all for today. We’ll have more exciting things to talk about in the future. Until then TTFN.

Related Resources

• Virtuoso RF Solution
• What’s New in Virtuoso (ICADVM18.1 Only)
• Virtuoso Electromagnetic Solver User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

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About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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(Sutirtha) Kabir