Taming Design Complexity in Chiplet-Based Automotive Electronics

22 Apr 2024 • 4 minute read

The automotive industry's transformation from a primarily mechanical domain to a highly technological one is remarkable. Once considered mere vehicles, cars are now advanced computers on wheels, embodying the shift from roaring engines to the quiet hum of processors due to semiconductor innovation. Peering under the hood of a modern car reveals an intricate network of electronic control units (ECUs) responsible for managing various aspects such as the engine, brakes, suspension, safety, infotainment, and Advanced Driver-Assistance Systems (ADAS). The increase in the number of ECUs is leading to high compute demands beyond the capability of traditional ECUs (monolithic ICs). The increasing complexity and computational demands drive the widespread adoption of chiplets, offering a scalable solution for high-performance computing needs. However, as vehicles become more connected and autonomous, the demand for sophisticated semiconductor solutions such as chiplets continues to rise, adding layers of intricacy to the design process.

Chiplets and Automotives: Luxury @ Increasing Complexity

Chiplets are becoming increasingly popular due to several factors, including the capability to accommodate more compute-intensive programs with excellent turnaround time and performance demands by AI applications and algorithms. As the automotive industry continues its march towards electrification, connectivity, and autonomy, the design complexity of chiplet-based automotive electronics will only escalate. Taming this increasing complexity demands performing system-level checks. To ensure the stringent safety and reliability requirements and optimal performance, package designers and designers face many challenges.

Challenges for Package Designers

Package designers face new challenges while pivoting to ultra-high-density foundry-based packaging technologies. A massive change for most package designs is the design verification step. Further, they face many other challenges, such as

Signoff DRC and LVS are standard practices when designing something for a foundry-based manufacturing process. Today, most package substrate designers use a much less formal process of validating their design from a DRC, LVS, and assembly perspective.
The lack of a formal SystemLVS methodology to validate alignment and connectivity through multiple 3D heterogeneously integrated package levels.
Pre- and post-route chiplet-to-chiplet signal integrity and compliance issues are a new requirement for most substrate designers focusing on single-die packaging. In single-die packages, electromagnetic (EM) extraction tools generate the pin parasitics of a package. In multi-chip(let) designs, the electrical compliance between the devices requires signal integrity expertise.

3DHI Challenges for ASIC/SoC Designers

A top-level planning methodology must be established to plan and optimize the interconnect (netlist) for system-level design across multiple chiplets and packaging tiers.
Robust co-design with the package substrate design team is paramount. The over-the-wall approach of the past may increase the final product cost or worse.
Pre-place and route thermal analysis capabilities to determine the best 2D and 3D chiplet placement to meet thermal budgets long before detailed implementation.
On-the-fly die splitting and repartitioning in the third dimension, potentially across different design nodes, requires a design tool that works concurrently with multiple PDKs or tech LEFs in a single layout session.

Existing Solutions

The industry has been using various solutions to deal with the increasing complexity.

The Point tools, extensive scripting, and disjointed solutions — underscore the challenges in synchronizing designs across various technology nodes and conducting comprehensive system-level verification. Thermal analysis emerges as a critical component of this process, necessitating meticulous attention at the IC, package, and system levels to mitigate risks such as the chimney effect, IR drop impacts, and performance degradation due to overheating.
Bunch of Wires (BoW) is an open PHY specification for die-to-die (D2D) parallel interfaces that can be implemented in organic laminate or advanced packaging technologies. With BoW, the D2D interfaces can be optimized to the host chiplet products, using minimal required features while supporting interoperability. A slice for BoW contains 16 data wires, a source-synchronous differential clock, and two optional signals – FEC (error control) and AUX (DBI, repair, control).
Universal Chiplet Interconnect Express (UCIe) is an open standard that prioritizes interoperability among general-purpose chiplets, just as was the intention in the BOW standard. This contrasts with HBM, which explicitly addresses data transfer involving DRAM stacks in 3D packages. It is focused on package aggregation. Here, interoperability is favored over design freedom, like PCIe.

How Cadence Simplifies Chiplet-Based Automotive Electronics Design

Semiconductor innovations coupled with advanced EDA tools from Cadence play a pivotal role in taming this complexity, enabling engineers to develop efficient, reliable, and safety-critical semiconductor solutions tailored to the demands of modern vehicles. By leveraging the latest advancements in semiconductor technology and embracing cutting-edge design methodologies, automotive chiplet designers can navigate the challenges posed by increasing complexity and drive innovation in the automotive industry for years.

Designing chiplet-based systems introduces complexities beyond individual fabric considerations. The system-level task requires applying electronic design automation (EDA) tools for thermal layer analysis, signal integrity, power integrity, and physical connectivity alignment. Cadence is a comprehensive solution provider offering IC, SiP/MCM, PCB, and system analysis tools.

Cadence Integrity 3D-IC Platform emerges as a unifying solution for disparate design platforms and tools. This platform facilitates collaborative work across different tools and platforms used by IC and package designers. Integrating analysis capabilities streamlines the design process, eliminating the need to merge databases. Cadence Allegro X Design Platform is a powerful tool that allows easy PCB design for laminate-based packages. The Integrity 3D-IC feature allows for stacking two silicon chips on top of each other. Additionally, Virtuoso is available for analog RF implementation. The implementation tools will remain the same and can be used for the single fabric and system. You can use analysis tools, such as Voltus for IR drop analysis, Celsius for thermal analysis, Clarity for advanced IC package extraction 3D EM simulation, and Sigrity for PCB level SI PI analysis. Click here to learn more about how you can use Cadence Analysis tools like Voltus for 3D-IC analysis and signoff.