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Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
The three-dimensional integrated circuit (3D-IC) technology revolutionizes the way we build our electronic marvels. In the domain of 3D-IC, chips and chiplets/die are stacked and interconnected, pushing the boundaries of power, performance, and efficiency.
It can be likened to a skyscraper for your gadgets, where every level brings astounding functionality. To serve the needs of continuous performance growth, building devices in the third dimension is becoming a widely accepted solution to reach "More than Moore."
While the benefits of the 3D-IC technology are significant, power analysis across multiple chiplets and into the system-level design presents new challenges. In this mini-series on 3DIC, we will delve into the 3D-IC design challenges and requirements, early exploration of power profiles of stacked dies before final implementation, power integrity signoff in 3DIC designs, and chip-centric thermal analysis.
3D-IC power integrity design is far more complex than the flat chip. Traditionally in 2D designs, Voltus Early Rail Analysis (ERA) has the ability to perform IR-drop analysis in the floorplanning stage. This requires designers to provide the power-grid planned design and current regions for power assignment. Such power estimation methods for 2D-ICs may not accurately capture the power characteristics for three-dimensional designs. In a 3D-IC design, three-dimensional power assignment, die stacking, inter-die connection, TSV planning, and combination of power grid in each die are all factors that a designer needs to consider. To design these factors, verifying the power integrity at the floorplan stage is no longer early enough. We need to analyze the rail during the system planning stage, even before any bumps are positioned or power grid is prepared.
The power delivery network that transports current to each die and across to other dies is one of the most significant aspects of 3D-IC. The performance of 3D-IC designs is heavily dependent on the power allocation, distribution, and IR drop effects among multiple dies. To design a 3D-IC, the design team needs to consider the three-dimensional aspect, which makes the design of stacking and inter-die net connections as critical steps. The high-capacity Integrity 3D-IC design and analysis platform, built on the infrastructure of Cadence’s leading InnovusTM Implementation System, is a valuable tool that aids in planning the 3D-IC system.
Here's a diagram illustrating the integrated solution for early rail analysis of 3D-IC designs:
The unified solution with the Integrity 3D-IC Platform, Innovus Implementation System, and Voltus IC Power Integrity Solution offers power grid optimization with early rail analysis and IR-aware implementation for individual dies and 3D-ICs.
Bumps and TSVs are used as vertical interconnects between chips. The quantity and placement of these TSVs and bumps have a significant impact on the reliability of the 3D-IC power grid. During the system design phase, it is imperative for designers to consider the required quantity or density of bumps and TSVs in different regions rather than precisely placing each TSV and bump. To optimize the number of TSVs and bumps, multiple iterations are often required. Each time the PG structure needs to be modified, the DEF file generation may take a considerable amount of time. However, Voltus provides an easy approach. By defining the number of bumps for different regions, Voltus can generate virtual bumps and establish connections between inter-die bumps if necessary. In the case of bumps located on the backside metal, pseudo TSVs are created to facilitate the connection between the backside metal and the frontside metal.
By getting early feedback from the 3D-IC ERA flow, designers can get the benefits of a robust power delivery structure and avoid over-design of individual chiplets. Through the Voltus 3D-IC ERA flow, you can complete system planning, PG specification, and rail analysis in one go, eliminating the need to handle the scripts and commands in multiple-point tools. This multi-chiplet design flow can significantly help shorten the time to tapeout without sacrificing design performance.
ERA Flow Using Integrity 3D-IC Platform
For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.
“Voltus Voice” showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.